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november 2008 rev 4 1/106 1 ST7FLCD1 8-bit mcu for lcd monitors with 60 kbytes flash, 2 kbytes ram, 2 ddc port s and infrared controller features 60 kbytes flash program memory in-circuit debugging and programming in-application programming data ram: up to 2 kbytes (256 bytes stack, 2 x 256 bytes for ddcs) 8 mhz, up to 9 mhz internal clock frequency true bit manipulation run and wait cpu modes programmable watchdog for system reliability protection against ille gal opcode execution 2 ddc bus interfaces with: ? ddc 2b protocol implemented in hardware ? programmable ddc ci modes ? enhanced ddc (eddc) address decoding ? hdcp encryption keys fast i2c single master interface 8-bit timer with programmable pre-scaler, auto- reload and independent buzzer output 8-bit timer with external trigger 4-channel, 8-bit analog to digital converter 4 + 2 8-bit pwm digital to analog outputs with frequency adjustment infrared controller (ifr) up to 22 i/o lines in 28-pin package 2 lines programmable as interrupt inputs master reset and low voltage detector (lvd) reset complete development support on pc windows full software package (a ssembler, linker, c- compiler and source level debugger) description the ST7FLCD1 is a microcontroller (mcu) from the st7 family with dedicated peripherals for lcd monitor applications. the ST7FLCD1 is an industry standard 8-bit core that offers an enhanced instruction set. the 5v supplied processor runs with an external clock at 24 mhz (27 mhz maximum). under software control, the mcu mode changes to wait mode thus reducing power consumption. the enhanced instruction set and addressing modes offer real programming potential. in addition to standard 8-bit data management, the mcu features also include true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. the device gathers the on-chip oscillator, cpu, 60-kbyte flash, 2-kbyte ram, i/os, two 8-bit timers, infrared preprocessor, 4-channel analog- to- digital converter, 2 ddcs, i2c single master, watchdog, reset and six 8-bit pwm outputs for analog dc control of external functions. so28 order code: ST7FLCD1 www.st.com obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
contents ST7FLCD1 2/106 contents 1 general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 central processing unit (cpu ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 low voltage detector and watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 watchdog or illegal operating code access reset . . . . . . . . . . . . . . . . . . . 23 3.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 reset procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 external interrupts (ita, itb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 peripheral interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3 program memory read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 icp (in-circuit programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 iap (in-application programming) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7 flash option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 contents 3/106 6 clocks and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.2 crystal oscillator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.3 external clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1.4 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.1 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3 exit from halt and wait modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.4 selected peripherals mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 common functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 8-bit analog-to-di gital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.2 procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 i2c single-master bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
contents ST7FLCD1 4/106 10.3 functional description (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4 transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.1 master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.4.2 master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11 display data channel interf aces (ddc) . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.1 ddc interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.1.1 hardware ddc2b interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.1.2 ddc/ci factory interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.1 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.2.2 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.3 ddc standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.3.1 ddc2b interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 11.3.2 mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 11.4 ddc/ci factory alignment interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.4.1 i2c modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.5 transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.6 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12 watchdog timer (wdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.2 main watchdog counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3 lock-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 12.5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13 8-bit timer (tima) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14 8-bit timer with external trig ger (timb) . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 contents 5/106 14.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 15 infrared preprocessor (ifr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 15.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 16 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 16.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 17 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 17.2 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 17.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 17.4 ac/dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 17.5 power on/off electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 17.6 8-bit analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.7 i2c/ddc bus electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 100 17.8 i 2 c/ddc bus timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 18 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.1 lead-free packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
general information ST7FLCD1 6/106 1 general information figure 1. st7lcd1 functional diagram address and data bus reset adc port d i 2 c pwm ram port b pa0...pa4 pb0/ain0 pd2 / ddc1-scl pd3 / ddc1-sda pd0 / i2c-scl pd1 / i2c-sda pd4 / ddc2-scl pd5 / ddc2-sda power 8-bit core alu control watchdog 60kbyte flash 2kbyte ddc2b vpp oscin oscout osc timer a pc1 / icc-data pd6 port c management ddc/ci pwm0...pwm4 pb1/ain1 lvd port a pa5/pwm5/buzou t pb2/ain2 pb3/ain3/ifr pc0 / icc-clk ST7FLCD1 5 v gnd ifr icd pd7 timer b pa6/ita/extrig pa7/itb table 1. abbreviations abbreviations description adc analog-to-digital converter alu arithmetical and logical unit cpu central processing unit ddc display data channel dma direct memory access i2c or iic inter-integrated circuit bus iap in-application programming icc in-circuit communication icp in-circuit programming ict in-circuit testing ifr infrared controller obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 general information 7/106 1.1 reference documents book: st7 mcu family manual cd: mcu on cd many libraries, software and applications notes are available. ask your stmicroelectronics sales office, your local support or search the company web site at www.st.com it interrupt lcd liquid crystal display lvd low voltage detector mcu microcontroller unit osc oscillator pwm pulse width modulator tim timer wdg watchdog table 1. abbreviations (continued) abbreviations description obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
general information ST7FLCD1 8/106 1.2 pin description figure 2. 28-pin small outline package (so28) pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 oscout oscin reset pb0/ain0 pb1/ain1 pb2/ain2 pb3/ain3/ifr pa0 /pw m0 pa1 /pw m1 pa2 /pw m2 pa3 /pw m3 pa4 /pw m4 pa5 /p wm 5 /buzo ut pa6/ita pa7/itb pd0/i2c-scl pd1/i2c-sda pd2/ddca-scl pd3/ddca-sda pd4/ddcb-scl pd5/ddcb-sda pd6 pd7 pc0/icc-clk pc1/icc-data vpp vss vdd table 2. 28-pin small outline package pin description pin pin name type description remark 1 oscout o oscillator input normal use at 24mhz 2 oscin i oscillator output 3 reset i/o reset 4 pb0/ain0 i/o port b0 or adc analog input 0 5 pb1/ain1 i/o port b1 or adc analog input 1 6 pb2/ain2 i/o port b2 or adc analog input 2 7 pb3/ain3/ifr i/o port b3 or adc analog input 3 or ifr input 8 pa0/pwm0 i/o port a0 or pwm output 0 9 pa1/pwm1 i/o port a1 or pwm output 1 10 pa2/pwm2 i/o port a2 or pwm output 2 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 general information 9/106 1.3 external connections figure 3 shows the recommended external connections for the device. the v pp pin is only used for programming or erasing the flash memory array, and must be tied to a 10 k pulldown resistor for normal operation. the 10 nf and 0.1 f decoupling capacitors on the power supply lines are a suggested emc performance/cost tradeoff. the external rc reset network (including the mandatory 1k serial resistor) is intended to protect the device against parasitic resets, especially in noisy environments. unused i/os should be tied high to avoid any unnecessary power consumption on floating lines. an alternative solution is to program the unused ports as inputs with pull-up. 11 pa3/pwm3 i/o port a3 or pwm output 3 12 pa4/pwm4 i/o port a4 or pwm output 4 13 pa 5 / p w m 5 / b u z out i/o port a5 or pwm output 5 or buzzer output 14 pa6/ita i/o port a6 or interrupt input a 15 pa7/itb i/o port a7 or interrupt input b 16 pd0/i2c-scl i/o port d0 or i2c serial bus clock 17 pd1/i2c-sda i/o port d1 or i2c serial bus data 18 pd2/ddca-scl i/o port d2 or ddca serial bus clock 19 pd3/ddca-sda i/o port d3 or ddca serial bus data 20 pd4/ddcb-scl i/o port d4 or ddcb serial bus clock 21 pd5/ddcb-sda i/o port d5 or ddcb serial bus data 22 pd6 i/o port d6 23 pd7 i/o port d7 24 pc0/icc-clk i/o port c0 or icc clock 25 pc1/icc-data i/o port c1 or icc data 26 vpp ps flash programming supply voltage normal op. mode: 0v (1) 27 vss ps ground 0v 28 vdd ps power supply 5v 1. this pin must be connected to a 10k pulldown resistor, see section 1.3 table 2. 28-pin small outline pa ckage pin description (continued) pin pin name type description remark obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
general information ST7FLCD1 10/106 figure 3. recommended external connections obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 general information 11/106 1.4 memory map figure 4. program memory map note: 1 refer to ta b l e 3 2 area ff00h to ffdfh is reserved in the event of icd use. 3 refer to ta b l e 4 table 3. hardware register memory map address block register label register name reset status remarks 0000h name namer circuit name register 00h read 0001h misc miscr miscellaneous register 00h r/w 0002h port a padr port a data register 00h r/w 0003h paddr port a data direction register 00h r/w 0004h port b pbdr port b data register 00h r/w 0005h pbddr port b data direction register 00h r/w 0006h port c pcdr port c data register 00h r/w 0007h pcddr port c data direction register 00h r/w 0008h port d pddr port d data register 00h r/w 0009h pdddr port d data direction register 00h r/w obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
general information ST7FLCD1 12/106 000ah adc adcdr adc data register 00h r 000bh adccsr adc control status register 00h r/w 000ch interrupt itrfre external interrupt register 00h r/w 000dh tima timcsra timer control st atus register 00h r/w 000eh timcpra timer counter preload register 00h r/w 000fh pwm pwmdcr0 8 bits pwm0 duty cycle register 00h r/w 0010h pwmdcr1 8 bits pwm1 du ty cycle register 00h r/w 0011h pwmdcr2 8 bits pwm2 du ty cycle register 00h r/w 0012h pwmdcr3 8 bits pwm3 du ty cycle register 00h r/w 0013h pwmcra pwm[0...3] control register 00h r/w 0014h pwmarra pwm[0...3] auto reload register ffh r/w 0015h pwmdcr4 8 bits pwm4 du ty cycle register 00h r/w 0016h pwmdcr5 8 bits pwm5 du ty cycle register 00h r/w 0017h pwmcrb pwm[4...5] control register 00h r/w 0018h pwmarrb pwm[4...5] auto reload register ffh r/w 0019h flash fcsr flash control/status register 00h r/w 001ah reserved 001bh wdg wdgcr watchdog control l register 7fh r/w 001ch i 2 c i2ccr i2c control register 00h r/w 001dh i2csr i2c status register 00h r 001eh i2cccr i2c clock control register 00h r/w 001fh i2cdr i2c data register 00h r/w 0020h ddc a ddccra ddc control register 00h r/w 0021h ddcsr1a ddc status 1 register 00h r 0022h ddcsr2a ddc status 2 register 00h r 0023h ddcoar1a ddc (7 bits) slave address 1 register 00h r/w 0024h ddcoar2a ddc (7 bits) slave address 2 register 00h r/w 0025h ddcdra ddc data register 00h r/w 0026h reserved 0027h ddcdcra ddc2b control register 00h r/w 0028h ddc b ddccrb ddc control register 00h r/w 0029h ddcsr1b ddc status 1 register 00h r 002ah ddcsr2b ddc status 2 register 00h r table 3. hardware register memory map (continued) address block register label register name reset status remarks obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 general information 13/106 002bh ddc b ddcoar1b ddc (7 bits) slave address 1 register 00h r/w 002ch ddcoar2b ddc (7 bits) slave address 2 register 00h r/w 002dh ddcdrb ddc data register 00h r/w 002eh reserved 002fh ddcdcrb ddc2b control register 00h r/w 0030h dm dmcr debug control register 00h r/w 0031h dmsr debug status register 10h r 0032h dmbk1h debug breakpoint 1 msb register ffh r/w 0033h dmbk1l debug breakpoint 1 lsb register ffh r/w 0034h dmbk2h debug breakpoint 2 msb register ffh r/w 0035h dmbk2l debug breakpoint 2 lsb register ffh r/w 0036h ifr ifrdr counter data register 00h r 0037h ifrcr control register 00h r/w 0038h timb timcsrb timer control st atus register 00h r/w 0039h timcprb timer counter preload register 01h r/w 003ah reserved table 3. hardware register memory map (continued) address block register label register name reset status remarks table 4. interrupt vector map vector address description remarks ffe0-ffe1h not used - ffe2-ffe3h timer a overflow interrupt vector internal interrupt ffe4-ffe5h timer b overflow interrupt vector internal interrupt ffe6-ffe7h not used - ffe8-ffe9h i 2 c interrupt vector internal interrupt ffea-ffebh itb interrupt vector external interrupt ffec-ffedh ita interrupt vector external interrupt ffee-ffefh ifr interrupt vector internal interrupt fff0-fff1h not used fff2-fff3h ddc2b b interrupt vector internal interrupt fff4-fff5h ddc/ci b interrupt vector internal interrupt fff6-fff7h ddc2b a interrupt vector internal interrupt fff8-fff9h ddc/ci a interrupt vector internal interrupt fffa-fffbh not used - obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
general information ST7FLCD1 14/106 fffc-fffdh trap (software) interrupt vector cpu interrupt fffe-ffffh reset vector - table 4. interrupt vector map (continued) vector address description remarks obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 central processing unit (cpu) 15/106 2 central processing unit (cpu) this cpu has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 2.1 main features enable executing 63 basic instructions fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) two 8-bit index registers 16-bit stack pointer 8 mhz cpu internal frequency (9 mhz max) low power modes: wait and halt maskable hardware interrupts non-maskable software interrupt 2.1.1 cpu registers the 6 cpu registers shown in figure 5 are not present in the memory mapping and are accessed by specific instructions. accumulator (a) the accumulator is an 8-bit general purpose register that holds operands and results of arithmetic and logic calculations. it also manipulates data. index registers (x and y) in indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation. (the cross-assembler generates a previous instruction (pre) to indicate that next instruction refers to y register.) the y register is not affected by interrupt automatic procedures (not pushed to and popped from the stack). program counter (pc) the program counter is a 16-bit register containing the address of next instruction the cpu executes. the program counter consists of two 8-bit registers: pcl (program counter low which is the lsb) pch (program counter high which is the msb). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
central processing unit (cpu) ST7FLCD1 16/106 figure 5. cpu registers condition code register (cc) read/write reset value: 111x1xxx the 8-bit condition code register contains the interrupt mask and four flags resulting from the instruction just executed. this register can also be handled by the push and pop instructions. these bits can be individually tested and/or controlled by specific instructions. bit 4 = h half carry this bit is set by hardware when a carry occurs between bits 3 and 4 of the alu during an add or adc instruction. it is reset by hardware during the same instructions. 0: no half carry has occurred. 1: a half carry has occurred. this bit is tested using the jr h or jrnh instruction. the h bit is useful in bcd arithmetic subroutines. note: instruction groups are defined in ta b l e 6 . bit 3 = i interrupt mask this bit is set by hardware when entering in interrupt or by software to disable all interrupts except the trap software interrupt. this bit is cleared by software. 0: interrupts are enabled. accumulator x index register y index register stack pointer condition code register program counter 70 1c 1 1 hi nz reset value = reset vector @ fffeh-ffffh 70 70 70 0 7 15 8 pch pcl 15 8 70 reset value = stack higher address reset value = 1x 1 1 x1 xx reset value = xxh reset value = xxh reset value = xxh x = undefined value 7 0 111hinzc obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 central processing unit (cpu) 17/106 1: interrupts are disabled. this bit is controlled by the rim, sim and iret instructions and is tested by the jrm and jrnm instructions. interrupts requested while i is set are latched and processed when i is cleared. by default an interrupt routine is not interruptible as i bit is set by hardware when you enter it and reset by the iret instruction at the end of interrupt routine. in case i bit is cleared by software during the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine. bit 2 = n negative this bit is set and cleared by hardware. it is re presentative of the result sign of the last arithmetic, logical or data manipulation. it is a copy of the 7 th bit of the result. 0: the last operation result is positive or null. 1: the last operation result is negative (i.e. the most significant bit is a logic 1). this bit is accessed by the jrmi and jrpl instructions. bit 1 = z zero this bit is set and cleared by hardware. this bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: the result of the last operation is different from zero. 1: the result of the last operation is zero. this bit is accessed by the jreq and jrne test instructions. bit 0 = c carry/borrow this bit is set and cleared by hardware and software. informs if an overflow or underflow occurred during the last arithmetic operation. 0: no overflow or underflow has occurred. 1: an overflow or underflow has occurred. this bit is driven by the scf and rcf in structions and tested by the jrc and jrnc instructions. it is also affected by the ?bit test and branch?, shift and rotate instructions. stack pointer (sp) read/write reset value: 01 ffh the stack pointer is a 16-bit register always pointing to the next free location in the stack.the pointer value increments when data is taken from the stack, it decrements once data is transfered into the stack (see figure 6 ). 15 8 00000001 7 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
central processing unit (cpu) ST7FLCD1 18/106 since the stack is 256 bytes deep, the most significant byte is forced by hardware. following an mcu reset, or after a reset stack pointer instruction (rsp), the stack pointer contains its reset value (the sp7 to sp0 bits are set) which is the stack highest address. the least significant byte of the stack pointer (called s) can be directly accessed by a ld instruction. note: when the lower limit is exceeded, the stack pointer wraps around stack upper limit, without indicating stack overflow. the previously stored information is then overwritten and therefore lost. stack also wraps in case of underflow. stack is used to save return address during a subroutine call and cpu context during interrupt. you can directly manipulate the stack using push and pop instructions. in case of interrupt, pcl is stored at the first location pointed to by the sp. other registers are then stored in the next locations as shown in figure 6 . when interrupt is received, the sp value decrements and the context is pushed to the stack. on return from interrupt, the sp value increments and the context is popped from the stack. a subroutine call and interrupt occupy two and five locations in the stack area respectively. figure 6. stack manipulation example sp sp sp sp sp sp call subroutine interrupt event push y pop y iret ret or rsp @ 01ffh @ 0100h stack higher address = 01ffh stack lower address = 0100h pcl pch cc a x pch pcl pch pcl cc a x pch pcl pch pcl y cc a x pch pcl pch pcl pcl pch table 5. instruction set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 load and transfer ld clr stack operation push pop rsp increment/decrement inc dec compare and tests cp tnz bcp logical operations and or xor cpl neg bit operations bset bres obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 central processing unit (cpu) 19/106 conditional bit test and branch btjt btjf arithmetic operations adc add sub sbc mul shift and rotates sll srl sra rlc rrc swap sla unconditional jump or call jra jrt jrf jp call callr nop ret conditional branch jrxx interruption management trap wfi halt iret code condition flag modification sim rim scf rcf table 5. instruction set (continued) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 6. instruction groups mnemo description function/example dst src h i n z c adc add with carry a = a + m + c a m h n z c add addition a = a + m a m h n z c and logical and a = a . m a m n z bcp bit compare a, memory tst (a . m) a m n z bres bit reset bres byte, #3 m bset bit set bset byte, #3 m btjf jump if bit is false (0) btjf byte, #3, jmp1 m c btjt jump if bit is true (1) btjt byte, #3, jmp1 m c call call subroutine callr call subroutine relative clr clear reg, m 01 cp arithmetic compare tst(reg - m) reg m n z c cpl one complement a = ffh-a reg, m nz 1 dec decrement dec y reg, m nz halt halt reset when wdg active 0 iret interrupt routine return pop cc, a, x, pc h i n z c obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
central processing unit (cpu) ST7FLCD1 20/106 inc increment inc x reg, m nz jp absolute jump jp [tbl.w] jra jump relative always jrt jump relative jrf never jump jrf * jrih jump if ext. interrupt = 1 jril jump if ext. interrupt = 0 jrh jump if h = 1 h = 1 ? jrnh jump if h = 0 h = 0 ? jrm jump if i = 1 i = 1 ? jrnm jump if i = 0 i = 0 ? jrmi jump if n = 1 (minus) n = 1 ? jrpl jump if n = 0 (plus) n = 0 ? jreq jump if z = 1 (equal) z = 1 ? jrne jump if z = 0 (not equal) z = 0 ? jrc jump if c = 1 c = 1 ? jrnc jump if c = 0 c = 0 ? jrult jump if c = 1 unsigned < jruge jump if c = 0 jmp if unsigned >= jrugt jump if (c + z = 0) unsigned > jrule jump if (c + z = 1) unsigned <= ld load dst <= src reg, m m, reg nz mul multiply x,a = x * a a, x, y x, y, a 00 neg negate (2's compl) neg $10 reg, m nz c nop no operation or or operation a = a + m a m n z pop pop from the stack pop reg reg m pop cc cc m h i n z c table 6. instruction groups (continued) mnemo description function/example dst src h i n z c obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 central processing unit (cpu) 21/106 push push onto the stack push y m reg, cc rcf reset carry flag c = 0 0 ret subroutine return rim enable interrupts i = 0 0 rlc rotate left true c c <= dst <= c reg, m nz c rrc rotate right true c c => dst => c reg, m nz c rsp reset stack pointer s = max allowed sbc subtract with carry a = a - m - c a m n z c scf set carry flag c = 1 1 sim disable interrupts i = 1 1 sla shift left arithmetic c <= dst <= 0 reg, m nz c sll shift left logic c <= dst <= 0 reg, m nz c srl shift right logic 0 => dst => c reg, m 0zc sra shift right arithmetic dst7 => dst => c reg, m nz c sub subtraction a = a - m a m n z c swap swap nibbles dst[7..4] <=> dst[3..0] reg, m nz tnz test for neg & zero tnz lbl1 n z trap s/w trap s/w interrupt 1 wfi wait for interrupt 0 xor exclusive or a = a xor m a m n z table 6. instruction groups (continued) mnemo description function/example dst src h i n z c obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
reset ST7FLCD1 22/106 3 reset the reset procedure provides an orderly software start-up or quits low power modes. three reset modes are provided: 1. low voltage detector reset, 2. watchdog or illegal op erating code access reset, 3. external reset at the reset pin. at reset, the reset vector is fetched from fffeh and ffffh addresses and loaded into the pc (the program execution starting from this point). an internal circuitry provides a 4096 cpu cl ock cycle delay as soon as that the oscillator becomes active. 3.1 low voltage detector and watchdog reset the low voltage detector circuitry generates a reset when: v dd is above v trm , v dd is below v trh when v dd is rising, v dd is below v trl when v dd is falling ( figure 7 ) figure 7. low voltage detector typical hysteresis (v trh -v trl ) of 250 mv this circuitry is active only when v dd is higher than v trm . during low voltage dete ctor reset, the reset pin is held low, thus permitting the mcu to reset other devices. during a watchdog reset, the reset pin is pulled low permitting the mcu to reset other devices as when low voltage ( figure 8 ). the reset cycle is pulled low during 500ns typically. reset v dd v trh v trl v trm obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 reset 23/106 figure 8. reset generation diagram 3.2 watchdog or illegal op erating code access reset for more information regarding the watchdog, refer to section 12 . an illegal opcode re set occurs if the mcu attempts to re ad and execute a co de that does not match a valid st7 instruction. 3.3 external reset the external reset is an active low input signal applied to reset pin of mcu. as shown in figure 9 , reset signal must remain low for a minimum of 1 s. internal schmitt trigger and filter provided at the reset pin improve noise immunity. 3.4 reset procedure at power-up, the mcu follows the sequence described in figure 9 . figure 9. reset timing diagram note: refer to electrical characteristics for values of t ddr , t oxov , v trh , v trl and v trm lvd reset reslvd v dd watchdog illegal opcode access external reset reset v dd oscin f cpu ffff fffe pc reset watchdog reset t ddr t oxov 4096 cpu clock cycles delay obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
interrupts ST7FLCD1 24/106 4 interrupts there are two different methods to interrupt the st7: 1. maskable hardware interrupts as listed in ta bl e 8 2. non-maskable software interrupt (trap). the interrupt processing flowchart is shown in figure 10 . only enabled maskable interrupts are serviced. however, disabled interrupts are latched and processed. for an interrupt to be serviced, pc, x, a and cc registers are saved onto the stack, interrupt mask (i bit of the condition code register) is set to prevent additional interrupts. y register is not automatically saved. the pc is then loaded with interrupt vector, the interrupt service routine runs (refer to ta bl e 8 for vector addresses) and ends with the iret instruction. with this letter, registers contents are recovered from the stack and normal processing resumes. note: i bit is then cleared providing that the corresponding bit stored in the stack is zero. though many interrupts can be run simultaneously, a priority order is defined (see ta bl e 8 ). the reset pin has the highest priority. if i bit is set, only trap interrupt is enabled. all interrupts allow the processor to exit wait low power mode. 4.1 software the software interrupt is the executable instruction trap. the interrupt is recognized when the trap instruction is executed, regardless of i bit state. when interrupt is recognized, it is serviced according to flowchart described in figure 10 . note: during icc communication the trap interrupt is reserved. 4.2 external interrupts (ita, itb) the ita (pa6), itb (pa7) pins generate an interrupt when a fa lling or rising edge occurs on these pins. these interrupts are enabled with itaite, itbite bits respectively, in itrfre register, also providing that i bit from cc register is reset. each external interrupt has an interrupt vector that uses itrfre register. 4.3 peripheral interrupts the various peripheral devices with interrupts include both display data channels (ddc a and ddc b), the infrared controller (ifr), two 8-bit timers (timer a and timer b) and the i2c interface. different peripheral interrupt flags fetch an interrupt if the i bit from the cc register is reset and the correspond ing enable bit is set. if any of these co nditions is not fulfilled, the interrupt is latched but not serviced , thus remaining pending. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 interrupts 25/106 4.4 processing interrupt flags are located in the status register. the enable bits are in the control register. when an enabled interrupt occurs, normal processing is suspended at the end of the current instruction execution. it is then serviced according to the flowchart from figure 10 . the general sequence for clearing an interrupt is an access to the status register while the flag is set followed by a read or write of an associated register. note that the clearing sequence resets the internal latch. a pending interrupt (i.e . waiting for being enabled) will therefore be lost if the clear sequence is executed. figure 10. interrupt processing flowchart from reset execute instruction restore pc, x, a, cc from stack interrupt? n y i bit set? n y fetch next instruction y n this clears i bit by default n y iret? stack pc, x, a, cc set i bit load pc from interrupt vector trap? obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
interrupts ST7FLCD1 26/106 4.5 register description external interrupt register (itrfre) read/write reset value:00h bit 7 =reserved. force by hardware to 0 . bit 6 =reserved. force by hardware to 0 . bit 5 = itbedge interrupt b edge selection. this bit is set and cleared by software. 0: falling edge detecte d on itb (default) 1: rising edge detected on itb bit 4 = itblat falling or rising edge detector latch. this bit is set by hardware, when a falling or rising edge, depending on the sensitivity, occurs on itb/pa7 pin. an interrupt is generated if itbite=1. it is cleared by software. 0: no edge detected on itb (default) 1: edge detected on itb bit 3 = itbite itb interrupt enable . this bit is set and cleared by software. 0: itb interrupt disabled (default) 1: itb interrupt enabled bit 2 = itaedge interrupt a edge selection. this bit is set and cleared by software. 0: falling edge detecte d on ita (default) 1: rising edge detected on ita bit 1 = italat falling or rising edge detector latch. this bit is set by hardware when a falling or a rising edge, depending on the sensitivity, occurs on ita/pa6 pin. an interrupt is generated if itaite=1. it is cleared by software. 0: no edge detected on ita (default) 1: edge detected on ita bit 0 = itaite ita interrupt enable . this bit is set and cleared by software. 0: ita interrupt disabled (default) 1: ita interrupt enabled table 7. external interrupt register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000ch 00h r/w itrfre 0 0 itb edge itblat itbite ita edge italat itaite 76543210 0 0 itbedge itblat itbite itaedge italat itaite obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 interrupts 27/106 ** many flags can cause an interrupt, see peripheral interrupt status register description. table 8. interrupt mapping source block description register label flag maskable vector address priority order reset reset n/a n/a no fffeh-ffffh trap software n/a n/a no fffch-fffdh not used fffah-fffbh ddc/ci a ddc interrupt ddcsr1a ddcsr2a ** yes fff8h-fff9h ddc2b a end of communication interrupt ddcdcra endcf yes fff6h-fff7h end of download interrupt edf yes fff6h-fff7h ddc/ci b ddc interrupt ddcsr1b ddcsr2b ** yes fff4h-fff5h ddc2b b end of communication interrupt ddcdcrb endcf yes fff2h-fff3h end of download interrupt edf yes fff2h-fff3h not used fff0h-fff1h ifr ifr interrupt ifrcr yes ffeeh-ffefh port a bit 6 external interrupt ita itrfre italat ffech-ffedh port a bit 7 external interrupt itb itrfre itblat yes ffeah-ffebh i2c i2c peripheral interrupts i2csr1 i2csr2 ** yes ffe8h-ffe9h not used ffe6h-ffe7h timb timer b overflow timcsrb tof yes ffe4h-ffe5h tima timer a overflow timcsra tof yes ffe2h-ffe3h not used ffe0h-ffe1h priority highest priority lowest obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
flash program memory ST7FLCD1 28/106 5 flash program memory the st7 dual voltage high density flash (hdflash) is a non-volatile memory that can be electrically erased as a single block or by in dividual sectors and programmed on a byte-by- byte basis using an external vpp supply. the hdflash devices can be programmed and erased off-board (plugged in a programming tool) or on-board using icp (in-circuit programming) iap (in-application programming). the array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. 5.1 main features three flash programming modes: ? insertion in a programming tool. in this mode, all sectors including option bytes can be programmed or erased ? icp (in-circuit programming). in this mode, all sectors including option bytes can be programmed or erased without removing the device from the application board. ? iap (in-application programming). in this mode, all sectors except sector 0 can be programmed or erased without removing the device from the application board and while the application is running. ict (in-circuit testing) for downloading and executing user application test patterns in ram read-out protection against piracy register access security system (rass) to prevent accidental programming or erasing 5.2 structure the flash memory is organized in sectors and can be used for both code and data storage. depending on the overall flash memory size in the microcontroller device, three user sectors are available. each sector is independently erasable. thus, complete erasing of the whole flash memory is avoided when only partial erasing is required. the first two sectors have a fixed size of 4 kbyte (see figure 11 ). they are mapped in the upper part of the st7 addressing space to the reset and interrupt vectors are located in sector 0 (f000h-ffffh). 5.3 program memory read-out protection the read-out protection is enabled through an option bit. when this option is selected, the programs and data stored in the program memory (flash or rom) are protected against read-out piracy (including a re-write protection). in flash devices, when this protection is removed by reprogramming the option byte, the entire program memory is first automatically erased. refer to the section 5.7 for more details. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 flash program memory 29/106 figure 11. memory map and sector address. 5.4 icp (in-circuit programming) to perform icp, the microcontroller must be switched to icc (in-circuit communication) mode by an external controller or programming tool. depending on the icp code downloaded in ram, flash memory programming can be fully customized (number of bytes to program, program locations or selection serial communication interface for downloading). when using a stmicroelectronics or third-party programming tool that supports icp and the specific microcontroller device, the user only needs to implement the icp hardware interface on the application board (see figure 12 ). for more details on the pin locations, refer to the device pin description. icp needs a minimum of 4 and up to 6 pins to be connected to the programming tool. these pins are: reset : device reset vss: device power supply ground icc-clk: icc output serial clock pin icc-data: icc input serial data pin vpp: programming voltage vdd: application board power supply note: 1 if the icc-clk or icc-data pins are only used as outputs in the application, no signal isolation is necessary. as soon as the programmin g tool is plugged to the board, even if an icc session is not in progress, the icc-clk an d icc-data pins are not available for the application. if they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. refer to the programming tool documentation for recommended resistor values. 2 during the icc session, the progra mming tool must control the reset pin. this can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5ma at high level (push pull output or pull-up resistor<1k). a schottky diode can be used to isolate the application reset circuit in this case. when using a classical rc network with r>1k or a reset management ic with open drain output and pull-up resistor>1k, no sector 1 sector 0 sector 2 60k dv flash ffffh efffh dfffh 1000h memory size 52 kbytes obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
flash program memory ST7FLCD1 30/106 additional components are needed. in all cases the user must ensure that no external reset is generated by the application during the icc session. 3 the use of pin 7 of the icc connector depends on the programming tool architecture. this pin must be connected when using most st programming tools (it is used to monitor the application power supply).. figure 12. typical icp interface 5.5 iap (in-application programming) this mode uses a boot loader program previously stored in sector 0 by the user (in icp mode or by plugging the device in a programming tool). this mode is fully controlled by user software. this allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored, etc.). for example, it is possible to download code from the spi, sci, usb or can interface and program it in the flash. iap mode can be used to program any of the flash sectors except sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. icc connector iccdata iccclk reset v dd he10 connector type application power supply 1 2 4 6 8 10 97 5 3 programming tool icc connector application board icc cable optional (see note 3) 10k v ss iccsel/vpp st7 c l2 c l1 oscin oscout optional see note 1 see note 1 see note 2 application reset source application i/o (see note 4) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 flash program memory 31/106 5.6 register description flash control/status register (fcsr) read/write reset value: 0000 0000 (00h) this register is reserved for use by programming tool software. it controls the flash programming and erasing operations. 5.7 flash option bytes each device is available for production in user programmable versions (flash) as well as in factory coded versions (rom). flash devices are shipped to customers with a default content (ffh), while rom factory coded parts contain the code supplied by the customer. this implies that flash devices have to be configured by the customer using the option bytes while the rom devices are factory-configured. the option bytes are used to select the hardware configuration of the microcontroller. they have no address in the memory map and can be accessed only in programming mode (for example using a standard st7 programming tool). the default content of the flash is fixed to ffh. to program directly the flash devices using icp, flash devices are shipped to customers with the internal rc clock source enabled. in masked rom devices, the option bytes are fixed in hardware by the rom code. static option byte 1 opt0= fmp_r flash memory read-out protection this option indicates if the user flash memory is protected against read-out piracy. this protection is based on a read and write protection of the memory in test modes and icp mode. erasing the option bytes when the fmp_r option is selected causes the whole user memory to be erased first. 0: read-out protection enabled 1: read-out protection disabled static option byte 2 76543210 00000000 76543210 fmp_r default11111111 76543210 default11111111 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
clocks and low power modes ST7FLCD1 32/106 6 clocks and low power modes 6.1 clock system 6.1.1 general description to operate, the device needs a number of clock signals. all clock signals derive from the root 24mhz clock signal ckxt provided at the output of the "osc" circuit (refer to figure 13 ). if a 24mhz quartz crystal is applied on pins oscin, oscout, the osc operates in a crystal- controlled oscillator mode. an ex ternal clock signal can also be applied on oscin pin, putting the osc in external clock mode operation. the block diagram in figure 13 shows the basic configuration of the clock system. figure 13. main clock generation 6.1.2 crystal oscillator mode in this mode, the root clock is generated by on-chip oscillator controlled by an external parallel fundamental-mode quartz crystal. general design precautions must be followed to ensure a maximum stabili ty. foot capacitors c l1 and c l2 must be adapted to match the crystal used. a 100kohms resistor is internally connected to oscin and oscout. note: if a murata ceramic resonator is to be used, murata recommends their ceralock? cstcgseries (fundamental type) with built-in cl1 and cl2 capacitors, such as:- cstcg24m0v51-r0 for 24-mhz external, 8-mhz internal clock operation cstcg27m0v51-r0 for 27-mhz external, 9-mhz internal clock operation no additional external capacitor is therefore needed with either model of this series. 6.1.3 external clock mode in this mode, an external clock is provided on pin oscin, while the oscout is left open ( figure 13 ). the signal is internally buffered before feeding the following stages. there is the same emphasis on stability of the external clock as in crystal oscillator mode. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 clocks and low power modes 33/106 6.1.4 clock signals the root clock is divided by factors of 3, to obtain cpu clock (f cpu ). figure 14. clock system diagram 6.2 power saving modes mcu offers the possibility to decrease powe r consumption at any time by software operation. 6.2.1 halt mode the halt mode is the mcu lowest power consumption mode. meanwhile, the halt mode also stops the oscillator stage completely which is the most critical condition (mcu cannot recover by itself). for this reason, the halt mode is not compatible with the watchdog protection: 6.2.2 wait mode this mode is a low power consumption mode. the wfi instruction sets the mcu in wait mode: the internal clock remains active but all cpu processing is stopped; however, all other peripherals still run. note: in wait mode dma (ddcs ) accesses are possible. 6.2.3 exit from halt and wait modes the mcu can exit halt mode at re ception of an external interrup t: ita or itb. the oscillator is then turned on and a stabiliz ing time is necessary before releasing cpu operation (4096 cpu clock cycles). after this delay, the cpu continues operation according to what caused its release, either by servicing an interrupt or by fetching the reset vector in case of reset. during wait mode, the i bit from the condition code register is cleared, enabling all interrupts. this leads the mcu to exit wait mode, the corresponding interrupt vector to be fetched, the interrupt routine to be executed and normal processing to resume. table 9. watchdog compatibility watchdog executing halt instruction enabled generates an immediate reset disabled puts the mcu in halt mode obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
clocks and low power modes ST7FLCD1 34/106 a reset causes the program counter to fetch the reset vector. processing starts as with a normal reset. figure 15. wait flow chart note: before servicing an interrupt, the cc register is pushed on the stack. the i-bit is set during the interrupt routine and cleared when the cc register is popped. if reset fetch reset vector or service interrupt mdp run mode n n interrupt reset wfi instruction 4096 cpu clock cycles delay y y mcu oscillator : on periph. clock : on cpu clock : on i-bit : cleared oscillator : on periph clock : on cpu clock : on i-bit : set obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 clocks and low power modes 35/106 6.2.4 selected peripherals mode some peripherals have an ?on/off ?bit to disconnect the block (or part of) and decrease the mcu power consumption (configuration by default at reset): table 10. peripheral modes bits register comment reset ports pxddi pxddr cut the output function pad (input mode) off adc adon adcsr cut analog consumption and clock off pwmi oei pwmcrx cut the pad consumption off ddc pe, ddc2bpe ddccr, ddcdcr off wdg wgda wdgcr cut the output reset off i2c pe i2ccr off obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i/o ports ST7FLCD1 36/106 7 i/o ports i/o ports are used to transfer data through digital inputs and outputs. for specific pins, i/o ports allow the input of analog signals or the input/output of alternate signals for on-chip peripherals (ddc, timer...). each pin can be independently programmed as digital input or output. each pin can be an analog input when an analog switch is connected to the analog digital converter (adc). figure 16. i/o pin critical circuit note: this is the typical i/o pin configuration. each port is customized with a specific configuration in order to handle certain functions. dr ddr latch latch data bus dr sel ddr sel v dd pa d analog switch (if required) analog enable (adc) alternate enable alternate enable digital enable alternate enable common analog rail alternate alternate input output p-buffer (if required) n-buffer 1 0 1 0 vss obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i/o ports 37/106 7.1 common functional description each port pin of the i/o ports can be individually configured as either input or output, under software control. each bit of data direction register (ddr) corresponds to an i/o pin of the associated port. this corresponding bit must be set to configure its associated pin as output and must be cleared to configure its associated pin as input. the data direction registers can be read and written. the typical i/o circuit is shown in figure 15 . any write to an i/o port updates the port data register even when configured as input. any read of an i/o port returns either the data latched in the port data register (pins configured as output) or the value of the i/o pins (pins configured as input). remark : when there is no i/o pin inside an i/o port, the returned value is logic (pin configured as input). at reset, all ddr registers are cleared, configuring all i/o ports as inputs. data registers (dr) are also cleared at reset. input mode when ddr=0, the corresponding i/o is configured in input mode. in this case, the output buffer is switched off, the state of the i/o is readable through the data register address, coming directly from the ttl schmitt trigger output and not from the data register output. output mode when ddr=1, the corresponding i/o is configured in output mode. in this case, the output buffer is activated according to the data register content. a read operation is directly performed from the data register output. analog input each i/o can be used as analog input by adding an analog switch driven by the analog digital converter. the i/o must be configured in input before using it as analog input. when the analog channel is selected by the adc the analog value is directly driven to the adc through an analog switch. alternate mode a signal coming from an on-chip peripheral is an output on the i/o, the latter then being automatically configured in output mode. table 11. i/o pin function ddr mode 0 input 1 output obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i/o ports ST7FLCD1 38/106 the signal coming from the peripheral enables the alternate signal to be output. a signal coming from an i/o can be input in an on-chip peripheral. an alternate input must first be configured in input mode (ddr=0). alternate and i/o input configurations are identical without pull-up. the signal to be input in the peripheral is taken after the ttl schmitt trigger when available. the i/o state is readable as in input mode by addressing the corresponding i/o data register. 7.2 port a each port a bit can be defined as an input line or as a push-pull. it can be also be used to output the pwm outputs. outputs pa4 and pa5 may also be configured as high current (8 ma) push-pull outputs by means of the miscr register. miscellaneous register (miscr) read/write reset value:00h bits [7:3] = reserved. forced by hardware to 0 . bit 2 = pa5ovd port a bit 5 overdrive table 12. port a descriptions port a i/o alternate function input (1) 1. reset state output signal condition pa0 with weak pull-up push-pull pwm0 oe0=1 (pwm) pa1 with weak pull-up push-pull pwm1 oe1=1 (pwm) pa2 with weak pull-up push-pull pwm2 oe2=1 (pwm) pa3 with weak pull-up push-pull pwm3 oe3=1 (pwm) pa4 with weak pull-up push-pull pwm4 oe4=1 (pwm) pa5 with weak pull-up push-pull pwm5 oe5=1 (pwm) with weak pull-up buzout buzen = 1 (timer a) (2) 2. if both pwm5 and buzout are enabled, buzout has priority over pwm5. pa6 with weak pull-up push-pull external interrupt ita see external interrupt register description pa7 with weak pull-up push-pull external interrupt itb 76543 2 1 0 00000pa5ovdpa4ovd0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i/o ports 39/106 this bit is set and cleared by software. it is used only if port a bit 5 is set as an output (paddr, pwm5 or buzout). it has no effect if set as an input. 0: 2 ma push-pull output 1: 8 ma push-pull output bit 1 = pa4ovd port a bit 4 overdrive this bit is set and cleared by software. it is used only if port a bit 4 is set as an output (paddr or pwm4). it has no effect if set as an input. 0: 2 ma push-pull output 1: 8 ma push-pull output bit 0 = reserved. must be cleared by software. figure 17. port a [5:0] obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i/o ports ST7FLCD1 40/106 figure 18. port a [7:6] 7.3 port b each port b bit can be used as the analog source to the analog digital converter. only one i/o line at a time must be configured as an analog input. pins levels are all limited to 5v. all unused i/o lines should be tied to an appropriate logic level (either v dd or v ss ). since adc and microprocessor are on the same chip and if high precision is required, the user should not switch heavily loaded signals during conversi on. such switching will affect the supply voltages used as analog references. the conversion accuracy depends on the quality of power supplies (v dd and v ss ). the user must take special care to ensure that a well regulated reference voltage is present on v dd and v ss pins (power supply variations must be less than 3.3v/ms). this implies, in particular, that a suitable decoupling capacitor is used at v dd pin. table 13. port b description port b i / o alternate function input* output signal condition pb0 with weak pull-up when digital input push-pull analog input (adc):ain0 adon = 1 & ch[1:0]=00 (adccsr) pb1 with weak pull-up when digital input push-pull analog input (adc) ain1 adon = 1 & ch[1:0]=01 (adccsr) pb2 with weak pull-up when digital input push-pull analog input (adc) ain2 adon = 1 & ch[1:0]=10 (adccsr) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i/o ports 41/106 figure 19. port b [2:0] pb3 with weak pull-up when digital input push-pull analog input (adc) ain3/ ifr adon = 1 & ch[1:0]=11 (adccsr) for analog input in this case, ifr is disabled *reset state table 13. port b description port b i / o alternate function input* output signal condition data bus dr sel ddr sel analog switch analog enable (adc) common analog rail 1 0 ttl schmitt trigger dr ddr latch latch v dd analog enable (adc) pad obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i/o ports ST7FLCD1 42/106 figure 20. port b [3] 7.4 port c the available port pins of port c may be used as general purpose i/o. note: these 2 pins are reserved for icc use during icc communication. if icc is not used at all, they can be used as general purpose i/os. data bus dr sel ddr sel analog switch analog enable (adc) common analog rail 1 0 ttl schmitt trigger dr ddr latch latch v dd analog enable (adc) pad alternate input table 14. port c description port c i / o alternate function input* output signal condition pc0 without pull-up open-drain pc1 without pull-up open-drain *reset state obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i/o ports 43/106 figure 21. port c 7.5 port d the alternate functions are: the i/o pins of the on-chip i2c scli & sdai for pd[1:0], the i/o pins of the on-chip ddca scld & sdad for pd[3:2], the i/o pins of the on-chip ddcb scld & sdad for pd[5:4] input and output on pd[7:6] data bus dr sel ddr sel 1 0 ttl schmitt trigger dr ddr latch latch v ss v dd table 15. port d description port d i / o alternate function input* output signal condition pd0 without pull-up open-drain scli (i nput with ttl schmitt trigger or open-drain output) i 2 c enable pd1 without pull-up open-drain sdai (i nput with ttl schmitt trigger or open-drain output) i 2 c enable pd2 without pull-up open-drain scld a (input with ttl schmitt trigger or open-drain output) ddc a enable pd3 without pull-up open-drain sdad a (input with ttl schmitt trigger or open-drain output) ddc a enable obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i/o ports ST7FLCD1 44/106 figure 22. port d 7.6 register description data registers (pxdr) data direction registers (pxddr) (x corresponds to an i/o pin of the associated port. in input mode the value is 00h by default). pd4 without pull-up open-drain scld b (input with ttl schmitt trigger or open-drain output) ddc b enable pd5 without pull-up open-drain sdad b (input with ttl schmitt trigger or open-drain output) ddc b enable pd6 without pull-up open-drain pd7 without pull-up open-drain *reset state table 15. port d description (continued) port d i / o alternate function input* output signal condition data bus dr sel ddr sel 1 0 ttl schmitt trigger dr ddr latch latch v ss alternate input alternate output enable alternate 1 0 output alternate output enable obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i/o ports 45/106 table 16. i/o ports register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0002h 00h r/w padr padr[7:0] 0003h 00h r/w paddr paddr[7:0] 0004h 00h r/w pbdr pbdr[7:0] 0005h 00h r/w pbddr pbddr[7:0] 0006h 00h r/w pcdr pcdr[7:0] 0007h 00h r/w pcddr pcddr[7:0] 0008h 00h r/w pddr pddr[7:0] 0009h 00h r/w pdddr pdddr[7:0] obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
pwm generator ST7FLCD1 46/106 8 pwm generator this pwm on-chip peripheral consists of two blocks, each one with its own 8-bit auto-reload counter. the first block (block a) outputs up to four separate pwm signals at the same frequency. the second block (block b) outputs up to two separate pwm signals at another frequency. each pwm output may be enabled or disabled independently of the other. the polarity of each pwm output may also be independently set. 8.1 main features two distinct programmable frequencies between 31.250 khz and 8 mhz resolution: t cpu 8.2 functional description the free-running 8-bit counter is fed by the cpu clock and increments on every rising edge of the clock signal. when a counter overflow occurs, the counter is automatically reloaded with the contents of the arr register. each pwmx output signal can be enabled independently using the corresponding oex bit in the pwm control register (pwmcr). when this bit is set, the corresponding i/o is configured as an output push-pull alternate function. pwm[3:0] all have the same frequency which is controlled by counter period a and the arra register value. f pwma = f countera / (256-arra) pwm[5:4] all have the same frequency which is controlled by counter period b and the arrb register value. f pwmb = f counterb / (256-arrb) when a counter overflow occurs, the pw mx pin level is toggled depending on the corresponding opx (output polarity) bit in the pwmcr register. when the counter reaches the value contained in one of the duty cycle registers (dcrix), the corresponding pwmx pin level is restored. this dcrix register can not be accessed directly , it is loaded from the duty cycle register (dcrx) at each overflow of the counter. this double buffering method prevents glitch generation when changing the duty cycle on the fly. note: the reload values will also affect the value and the resolution of the duty cycle of the pwm output signal. to obtain a signal on a pwmx pin, the contents of the dcrx register must be greater than or equal to the contents of the arr register. the maximum available resolution for duty cycle is 1/(256-arr). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 pwm generator 47/106 figure 23. pwm block diagram figure 24. pwm generation figure 25. pwm generation table 17. pulse width in t cpu pulse width in t cpu dcr > arr dcr - arr + 1 dcr = arr 1 dcr < arr 0 (output will not toggle) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
pwm generator ST7FLCD1 48/106 this pulse width modulated signal must be filt ered, using an external rc network placed as close as possible to the associated pin. this provides an analog voltage proportional to the average charge through the external capacitor. thus for a higher mark/space ratio (high time much greater than low time) the average output voltage is higher. the external components of the rc network should be selected for the filtering level required for control of the system variable. with: r ext = 1 k f pwm = f cpu / (256 - arr) f cpu = 8mhz v dd = 5v worst case, pwm duty cycle 50% table 18. 8-bit pwm ripple after filtering c ext v ripple 470 nf 60 mv 1 f 27 mv 4.7 f6 mv obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 pwm generator 49/106 figure 26. pwm simplified voltage output after filtering 8.3 register description each pwm is associated with two control bits (oex and opx) and a control register (dcrx). table 19. pwm register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00fh 00h r/w pwmdcr0 dcr0[7:0] 0010h 00h r/w pwmdcr1 dcr1[7:0] 0011h 00h r/w pwmdcr2 dcr2[7:0] 0012h 00h r/w pwmdcr3 dcr37:0] 0013h 00h r/w pwmcra oe3 oe2 oe1 oe0 op3 op2 op1 op0 0014h ffh r/w pwmarra arra[7:0] 0015h 00h r/w pwmdcr4 dcr4[7:0] 0016h 00h r/w pwmdcr5 dcr5[7:0] 0017h 00h r/w pwmcrb 0 0 oe5 oe4 0 0 op5 op4 0018h ffh r/w pwmarrb arrb[7:0] obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
pwm generator ST7FLCD1 50/106 duty cycle registers (pwmdcrx) read/write reset value 0000 0000 (00h) bits [7:0] = dc[7:0] duty cycle data these bits are set and cleared by software. a dcrx register is associated with the dcrix register of each pwm channel to determine the second edge location of the pwm signal (the first edge location is common to all 4 channels and given by the arr register). these dcr registers allow the duty cycle to be set independently for each pwm channel. control register a (pwmcra) read/write reset value: 0000 0000 (00h) bits [7:4] = oe [3:0] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels independently acting on the corresponding i/o pin. 0: the pwm pin is a general i/o. 1: the pwm pin is driven by the pwm peripheral. bits [3:0] = op[3:0] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the 4 pwm output signals. 0: positive polarity. 1: negative polarity. note: when an opx bit is modified, the pwmx output signal is immediately updated. auto-reload register a (pwmarra) read/write reset value: 1111 1111(ffh) bits [7:0] = ar[7:0] counter auto-reload data 76543 2 1 0 dc7 dc6 dc5 dc4 dc3 dc2 dc1 dc0 76543 2 1 0 oe3 oe2 oe1 oe0 op3 op2 op1 op0 76543 2 1 0 ar73 ar6 ar5 ar4 ar3 ar2 ar1 ar0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 pwm generator 51/106 these bits are set and cleared by software. they are used to hold the auto-reload valu which is automatically loaded in the counter when an overflow occurs. writing in this register reload the pwm counter to arr a value. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register adjusts the pwm frequency (setting the pwm duty cycle resolution) for outputs pwm[3:0]. control register b (pwmcrb) read/write reset value: 0000 0000 (00h) bits [7:6] = reserved . forced by hardware to 0 bits [5:4] = oe[5:4] pwm output enable these bits are set and cleared by software. they enable or disable the pwm output channels independently acting on the corresponding i/o pin. 0: the pwm pin is a general i/o. 1: the pwm pin is driven by the pwm peripheral. bits [3:2] = reserved. forced by hardware to 0 bit [1:0] = op[5:4] pwm output polarity these bits are set and cleared by software. they independently select the polarity of the 4 pwm output signals. 0: positive polarity. 1: negative polarity. note: when an opx bit is modified, the pwmx output signal is immediately reversed. auto-reload register b (pwmarrb) read/write reset value: 1111 1111 (ffh) bits [7:0] = ar [7:0] counter auto-reload data these bits are set and cleared by software. they are used to hold the auto-reload value which is automatically loaded in the counter when an overflow occurs. writing in this register reload the pwm counter to arr b value. at the same time, the pwm output levels are changed according to the corresponding opx bit in the pwmcr register. this register adjusts the pwm frequency (by setting the pwm duty cycle resolution) for outputs pwm[5:4]. 76543 2 1 0 0 0 oe5 oe4 0 0 op5 op4 76543 2 1 0 ar73 ar6 ar5 ar4 ar3 ar2 ar1 ar0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
8-bit analog-to-digital converter (adc) ST7FLCD1 52/106 9 8-bit analog-to-digital converter (adc) the on-chip analog to digital converter (adc) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. this peripheral has up to 4 multiplexed analog input channels (refer to device pin out description) that allows the peripheral to convert the analog voltage levels from up to 4 different sources. the result of the conversion is stored in a 8-bit data register. the a/d converter is controlled through a control/status register. figure 27. adc block diagram 9.1 main features 8-bit conversion up to 4 channels with multiplexed input linear successive approximation data register (dr) whic h contains the results conversion complete status flag on/off bit (to reduce power consumption) 9.2 functional description the high and low level reference voltages are v dd and v ss , respectively. consequently, conversion accuracy is degraded by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. 9.2.1 characteristics the conversion is monotonic, the result never decreases or increases if the analog input does not also drecrease or increase. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 8-bit analog-to-digital converter (adc) 53/106 if the input voltage is greater than or equal to v dd (voltage reference high), the results are equal to ffh (full scale) without overflow indication. if the input voltage is less than or equal to v ss (voltage reference low), the results are equal to 00h. the a/d converter is linear, the digital result of the conversion is given by the formula: the conversion accuracy is described in section 17 . when the a/d converter is continuously ?on?, the conversion time is 16 adc clock cycles which corresponds to 64 cpu clock cycles. the internal circuitry is in auto-calibration during the conversion cycle. this process prevents offset drifts. still, calibration cycles are required at start-up or after any a/d converter re-start. 9.2.2 procedure refer to the csr and sr registers in section 9.3 for the bit definitions. at start-up, the a/d converter is off (adon bit equal to ?0?). prior to using the a/d converter, the analog input ports must be configured as inputs (refer to section 7 ). using these pins as analog inputs does not affect the ability to read the port as a logic input. then, the adon bit must be set to 1. as internal ad circuitry starts calibration, it is mandatory to respect the stabiliz ing time (several tens of m illiseconds) prior to using a/d results. in the csr register, bits ch1 to ch0 select the analog channel to be converted (see ta bl e 2 0 ). these bits are set and cleared by software. the a/d converter performs a continuous conversion of the selected channel. when a conversion is complete, the coco bit is set by hardware, but no interrupt is generated. the result is written in the dr register. reading the dr result regi ster resets the coco bit. writing to the csr register aborts the current conversion, the coco bit is reset and a new conversion is started. note: resetting the adon bit disables the a/d converter. thus, power consumption is reduced when no conversions are needed. note: the a/d converter is not affected by wait mode. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
8-bit analog-to-digital converter (adc) ST7FLCD1 54/106 9.3 register description control/status register (adccsr) read/write reset value: (00h) bit 7 = coco conversion complete this bit is set by hardware. it is cleared by software by reading the result in the dr register or writing to the csr register. 0: conversion is not complete (default) 1: conversion can be read from the dr register. bit 6 = reserved . this bit must be cleared by software. bit 5 = adon a/d converter on this bit is set and cleared by software. 0: a/d converter is switched off (default) 1: a/d converter is switched on note: remember that the adc needs time to stabilize after the adon bit is set. bits [4:2] = reserved. forced to 0 by hardware. bits [1:0] = ch[1:0] channel selection. these bits are set and cleared by software. they select the analog input to be converted. table 20. adc register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00ah 00h r adcr ad[7:0] 00bh 00h r/w adccsr coco 0 adon 0 0 0 0 ch[1:0] 76543 2 1 0 coco 0 adon 0 0 0 ch1 ch0 table 21. channel selection pin ch1 ch0 ain0 (default) 0 0 ain1 0 1 ain2 1 0 ain3 1 1 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 8-bit analog-to-digital converter (adc) 55/106 data register (adcdr) read only reset value: (00h) bits [7:0] = ad[7:0] analog converted value this register contains the converted analog value in the range 00h to ffh. reading this register resets the coco flag. 76543 2 1 0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i2c single-master bus interface ST7FLCD1 56/106 10 i 2 c single-master bus interface the i2c bus interface serves as an interface between the microcontroller and the serial i2c bus. it provides single-master functions, an d controls all i2c bus-specific sequencing, protocol and timing. it supports fast i2c mode (400 khz) and up to 800 khz for certain applications. 10.1 main features parallel / i2c bus protocol converter interrupt generation standard i2c mode/fast i2c mode (up to 800 khz for certain applications) 7-bit addressing i2c single master mode end of byte transmission flag transmitter /receiver flag clock generation 10.2 general description in addition to receiving and transmitting data, this interface converts data from serial to parallel format and vice versa, using either an interrupt or a polled handshake. the interrupts are enabled or disabled by software. the interface is connected to the i2c bus by a data pin (sdai) and by a clock pin (scli). it can be connected both with a standard i2c bus and a fast i2c bus. this se lection is made by software. mode selection the interface can operate in the two following modes: 1. master transmitter/receiver, 2. idle (default). the interface automatically switches from idle to master mode after it generates a start condition and from master to idle mode after it generates a stop condition. communication flow the interface initiates a data transfer and generates the clock signal. a serial data transfer always begins with a start condition and ends with a stop condition. both start and stop conditions are generated by software. data and addresses are transferred as 8-bit bytes, msb first. the first byte following the start condition is the address byte. a 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter (see figure 28 ). acknowledge is enabled and disabled by software. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i2c single-master bus interface 57/106 the speed of the i2c interface is selected as standard (0 to 100 khz) and fast i2c (100 to 400 khz) and up to 800 khz for certain applications. figure 28. i 2 c bus protocol sda/scl line control transmitter mode : the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the data register. receiver mode : the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the data register. the scl frequency (f scl ) is controlled by a programmable clock divider which depends on the i2c bus mode. when the i2c cell is enabled, the sda and scl ports must be configured as a floating open- drain output or a floating input. in this case, the value of the external pull-up resistor used depends on the application. when the i2c cell is disabled, the sda and scl ports revert to being standard i/o port pins. figure 29. i 2 c interface block diagram obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i2c single-master bus interface ST7FLCD1 58/106 10.3 functional description (master mode) by default, the i2c interface operates in idle mode (m/idl bit is cleared) except when it initiates a transmit or receive sequence. to switch from default idle mode to master mode a start condition must be generated. setting the start bit causes the interface to switch to master mode (m/idl bit set) and generates a start condition. once the start condition is sent, the evf and sb bits are set by hardware and an interrupt is generated if the ite bit is set. then the master waits for a read of the sr register followed by a write in the dr register with the slave address byte, holding the scl line low (ev1). then the slave address byte is sent to the sda line via the internal shift register. after completion of this transfer (and the reception of an acknowledge from the slave if the ack bit is set), the evf bit is set by hardware and an interrupt is generated if the ite bit is set. then the master waits for a read of the sr register followed by a write in the cr register (for example set pe bit), holding the scl line low (ev2). next the master must enter receiver or transmitter mode. 10.4 transfer sequencing 10.4.1 master receiver following the address transmission and after sr and cr registers have been accessed, the master receives bytes from the sda line into the dr register via the internal shift register. after each byte the interface generates in sequence: an acknowledge pulse if the ack bit is set evf and btf bits are set by hardware with an interrupt if the ite bit is set then the interface waits for a read of the sr register followed by a read of the dr register, holding the scl line low (ev3). to close the communication, before reading the last byte from the dr register, set the stop bit to generate the stop condition. the interface automatically returns to idle mode (m/idl bit cleared). note: in order to generate the non-acknowledge pulse after the last received data byte, the ack bit must be cleared just before reading the second last data byte. 10.4.2 master transmitter following the address transmission and after sr register has been read, the master sends bytes from the dr register to the sda line via the internal shift register. the master waits for a read of the sr register followed by a write in the dr register, holding the scl line low (ev4). when the acknowledge bit is received, the interface sets the evf and btf bits with an interrupt if the ite bit is set. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i2c single-master bus interface 59/106 to close the communication, after writing the last byte to the dr register, set the stop bit to generate the stop condition. the interface automatically returns to idle mode (m/idl bit cleared). error case: af : detection of a non-acknowledge bit. in this case, the evf and af bits are set by hardware with an interrupt if the ite bit is set. to resume, set the start or stop bit. note: the scl line is not held low if af = 1. figure 30. transfer sequencing ev1: evf = 1, sb = 1, cleared by reading the sr register followed by writing to the dr register. ev2: evf = 1, cleared by reading the sr register followed by writing to the cr register (for example pe = 1). ev2-1: evf = 1, af = 1, cleared by reading the sr register followed by writing stop = 1 in the cr register. ev3: evf = 1, btf = 1, cleared by reading the sr register followed by reading the dr register. ev3-1 : same as ev3, but ack bit in cr register must be cleared before reading the dr register in order to send a nak pulse after the ?data n? byte. ev3-2 : same as ev3, but stop = 1 must be written in the cr register. ev4 : evf = 1, btf = 1, cleared by reading the sr register followed by writing to the dr register. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i2c single-master bus interface ST7FLCD1 60/106 figure 31. event flags and interrupt generation 10.5 register description i2c control register (i2ccr) read / write reset value: 0000 0000 (00h) bits [7:6] = reserved. forced to 0 by hardware. bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: master capability note: when pe = 0, all the bits of the cr register and the sr register except the stop bit are reset. all outputs are released when pe = 0. when pe = 1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i2c interface, write the cr register twice with pe = 1 as the first write only activates the interface (only pe is set). bit 4 = reserved. forced to 0 by hardware table 22. i 2 c register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001ch 00h r/w i2ccr 00 pe 0 start ack stop ite 001dh 00h r i2csr evf af tra 0 btf 0 m/idl sb 001eh 00h r/w i2cccr fm/ sm filt off cc[5:0] 001fh 00h r/w i2cdr dr[7:0] 76543 2 1 0 00pe0startackstopite obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i2c single-master bus interface 61/106 bit 3 = start generation of a start condition . this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe = 0) or when the start condition is sent (with interrupt generation if ite = 1). in master mode: 0: no start generation 1: repeated start generation in idle mode: 0: no start generation 1: start generation when the bus is free bit 2 = ack acknowledge enable . this bit is set and cleared by software. cleared by hardware when the interface is disabled (pe = 0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop generation of a stop condition . this bit is set and cleared by software. it is al so cleared by hardware when the interface is disabled (pe = 0) or when the stop condition is sent. in master mode only: 0: no stop generation 1: stop generation after the current byte transfer or after the current start condition is sent. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe = 0). 0: interrupt disabled 1: interrupt enabled i2c status register (i2csr) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event occurs. it is cleared by software by reading the sr register in case of error event or as described in section 10.5: transfer sequencing . it is also cleared by hardware when the interface is disabled (pe = 0). 0: no event 1: one of the following events has occurred: btf = 1 (byte received or transmitted) sb = 1 (start condition generated) 76543 2 1 0 evf af tra 0 btf 0 m/idl sb obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i2c single-master bus interface ST7FLCD1 62/106 af = 1 (no acknowledge received after byte transmission if ack = 1) address byte successfully transmitted. bit 6 = af acknowledge failure. this bit is set by hardware w hen no acknowledge is returned. an interrupt is generated if ite = 1. it is cleared by software by reading the sr register or by hardware when the interface is disabled (pe = 0). the scl line is not held low when af = 1. 0: no acknowledge failure 1: acknowledge failure bit 5 = tra transmitter/receiver. when btf is set, tra = 1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware when the interface is disabled (pe = 0). 0: data byte received (if btf = 1) 1: data byte transmitted bit 4 = reserved. forced to 0 by hardware . bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite = 1. it is cleared by software by reading the sr register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe= 0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse. in case an address byte is sent, this bit is set only after the ev2 event (see section 10.4 ). btf is cleared by reading sr register followe d by writing the next byte in dr register. following a byte reception, this bit is set afte r transmission of the acknowledge clock pulse if ack = 1. btf is cleared by reading sr register followed by reading the byte from dr register. the scl line is held low when btf = 1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = reserved. forced to 0 by hardware . bit 1 = m/idl master/idle. this bit is set by hardware when the interface is in master mode (writing start = 1). it is cleared by hardware after a stop condition on the bus. it is also cleared by hardware when the interface is disabled (pe = 0). 0: idle mode 1: master mode bit 0 = sb start bit. this bit is set by hardware when a start condition is generated (following a write start = 1). an interrupt is generated if ite = 1. it is cleared by software by reading the sr register obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 i2c single-master bus interface 63/106 followed by writing the address byte in dr register. it is also cleared by hardware when the interface is disabled (pe = 0). 0: no start condition 1: start condition generated i2c clock control register (i2cccr) read / write reset value: 0000 0000 (00h) bit 7 = fm/sm fast/standard i2c mode. this bit is set and cleared by software. it is not cleared when the interface is disabled (pe = 0). 0: fast i2c mode 1: standard i2c mode bit 6 = filtoff filter off. this bit is set and cleared by software, it is not taken into account in the emu version and is considered as always set to 1 (inactive filter). when set, it disables the filter of the i2c pads in order to achieve speeds of over 400 khz on a shortlength i2c bus (at the us er?s responsibility). such high frequencies are computed with the fast mode formula given below. bits [5:0] = cc[5:0] 6-bit clock divider. these bits select the speed of the bus (f scl ) depending on the i2c mode. they are not cleared when the interface is disabled (pe = 0). the value of the 6-bit clock divider, cc[5:0], 03h fast mode (fm/sm = 0): f scl > 100 khz f scl = f cpu /([2x([cc5...cc0]+3)]+1) standard mode (fm/sm = 1): f scl . 100 khz f scl = f cpu /(3x([cc5...cc0]+3)) note: the programmed f scl speed assumes that there is no load on the scl and sda lines. i2c data register (i2cdr) read / write reset value: 0000 0000 (00h) 76543 2 1 0 fm/sm filtoff cc5 cc4 cc3 cc2 cc1 cc0 76543 2 1 0 d7 d6 d5 d4 d3 d2 d1 d0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
i2c single-master bus interface ST7FLCD1 64/106 bits [7:0] = d[7:0] 8-bit data register . these bits contain the byte to be received or transmitted on the bus. transmitter mode : bytes are automatically transmitted when the software writes to the dr register. receiver mode : the first data byte is automatically received in the dr register using the least significant bit of the address. then, the subsequent data bytes are received one-by-one after reading the dr register. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 65/106 11 display data channel interfaces (ddc) the ddc (display data channel) bus interfaces are mainly used by the monitor to identify itself to the video controller, by the monitor manufacturer to perform factory alignment, and by the user to adjust the monitor?s parameters. both ddc interfaces consist of: a fully hardware-implemented interface, supporting ddc2b (vesa specification 3.0 compliant). it accesses the st7 on-chip memory directly through a built-in dma engine. a second interface, supporting the slave i2c functions for handling ddc/ci mode (ddc2bi), factory alignment, hdcp, enhan ced ddc (eddc) or other addresses by software. each ddc interface has its own dedicated dma area in ram. in the event of concurrent dma accesses, the ddc a cell has priority over the ddc b cell. 11.1 ddc interface features 11.1.1 hardware ddc2 b interface features full hardware support for ddc2b commun ications (vesa specif ication version 3) hardware detection of ddc2b addresses a0h/a1h separate mapping of edid version 1: base (128 bytes) and extended (128 bytes) support for error recovery mechanism detection of misplaced start and stop conditions random and sequential i2c byte read modes dma transfer from any memory location and to ram automatic memory address increment end of data downloading fl ag, end of communic ation flag and in terrupt capability 11.1.2 ddc/ci factory interface features general i2c features parallel bus /i2c protocol converter interrupt generation standard i2c mode 7-bit addressing obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 66/106 i2c slave features i2c bus busy flag start bit detection flag detection of misplaced start or stop condition transfer problem detection address matched detection 2 programmable address detection and/or hardware detection of ddc/ci addresses (6eh/6fh) end of byte transmission flag transmitter/receiver flag stop condition detection figure 32. ddc interface overview obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 67/106 figure 33. ddc interface block diagram 11.2 signal description 11.2.1 serial data (sda) the sda bidirectional pin is used to transfer data in and out of the device. an external pull- up resistor must be connected to the sda line. its value depends on the load of the line and the transfer rate. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 68/106 11.2.2 serial clock (scl) the scl input pin is used to synchronize all data in and out of the device when in i2c bidirectional mode. an external pull-up resistor must be connected to the scl line. its value depends on the load of the line and the transfer rate. note: when the ddc2b and ddc/ci factory interf aces are disabled (hwpe bit = 0 in the dcr register and pe bit = 0 in the cr register), the sda and scl pins revert to being standard i/o pins. 11.3 ddc standard the ddc standard is divided into several data transfer protocols: ddc2b, ddc/ci and other slave communication standards (hdcp, e-ddc, etc.). for ddc2b, refer to the ?vesa ddc standard v3.0 ? specification. for ddc/ci refer to the ?vesa ddc commands interface v1.0? ddc2b is a unidirectional channel from display to host. the host computer uses base-level i2c commands to read the edid data from the display which is always in slave mode. ddc/ci is a bidirectional chan nel between the host computer and the display. the ddc/ci offers a display control interface based on i2c bus. only the ddc2bi interface is supported (and not the ddc2b+ or ddc2ab interfaces). 11.3.1 ddc2b interface the ddc2b interface acts as an i/o interface between a ddc bus and the mcu memory. in addition to receiving and transmitting serial data, this interface directly transfers parallel data to and from memory using a dma engine, only ha lting cpu activity for 2 clock cycles during each byte transfer. the interface supports the following by hardware: ddc2b communication protocol write operations into ram read operations from ram in ddc2b mode, it operates in i2c slave mode. device addresses a0h/a1h are recognized. edid version 1 is used. the write and read operations allow the edid data to be downloaded during factory ali ment (for example). writing to the memory by the dma engine is inhibited by the wp bit in the dcr register. a write of the last data structure byte sets a flag and may be programmed to generate an interrupt request. the data address (sub-address) is either the second byte of write transfers or is pointed to by the internal address counter which automatically increments after each byte transfer. the physical address mapping of the data structure is fixed by hardware in a dedicated ram area (see ta bl e 2 5 ). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 69/106 11.3.2 mode description ddc2b mode: the ddc2b interface enters ddc2b mo de from the initial state if the software sets the hwpe bit. once in ddc2b mode, the interface always acts as a slave following the protoc ol described in figure 34 . the ddc2b interface continuously monitors the sda and scl lines for a start condition and will not respond (no acknowle dge) until one is found. a stop condition at the end of a read command (after a nack) forces the stand-by state. a stop condition at the end of a write command triggers the internal dma write cycle. the interface samples the sda line on the rising edge of the scl signal and outputs data on the falling edge of the scl signal. in any case , the sda line can only change when the scl line is low. figure 34. ddc2b protocol example figure 35. ddc1/2b operation flowchart edid data structure mapping: an internal address pointer defines the memory location being addressed. it defines the 256-byte block within the ram address space containing the data structure. the lsb is loaded with the data address sent by the master after a write device address. it defines the byte within the data structure currently addressed. it is reset upon entry into the ddc2b mode. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 70/106 figure 36. mapping of ddc2b data structure write operation once the ddc2b interface has acknowledged a write transfer request, i.e. a device address with rw = 0, it waits for a data address. when the latter is received, it is acknowledged and loaded into the lsb. then, the master may send any number of data bytes that are all acknowledged by the ddc2b interface. the data bytes are written in ram if the wp bit = 0 in the dcr register, otherwise the ram location is not modified. write operations are always performed in ram and therefore do not delay ddc transfers. meanwhile, concurrent software exec ution is halted for 2 clock cycles. figure 37. write sequence read operations all read operations consist of retrieving the da ta pointed to by an internal address counter which is initialized by a dummy write and which increments with any read. the ddc2b interface always waits for an acknowledge during the 9th bit-time. if the master does not pull the sda line low during this bit-time, the ddc2b interface ends the transfer and switches to a stand-by state. current address read: after generating a start condition the master sends a read device address (rw = 1). the ddc2b interface acknow ledges this and outp uts the data byte pointed to by the internal address pointer which subsequently increments. the master must not acknowledge this byte and must terminate the transfer with a stop condition. random address read: the master performs a dummy write to load the data address into the pointer lsb. then the master sends a restart condition followed by a read device address (rw = 1). sequential address read: this mode is similar to the current and random address reads, except that the master does acknowledge the data byte for the ddc2b interface to output obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 71/106 the next byte in sequence. to terminate the read operation the master must not acknowledge the last data byte and must generate a stop condition. the data output are issued from consecutive memory addresses. end of communication : upon a detection of nack or stop conditions at the end of a read transfer, the bit endcf is set and an interrupt is generated if endce is set. figure 38. read sequences read and write operations after each byte transfer, the internal address counter automatically increments. if the counter is pointing to the top of the structure, it rolls over to the bottom since the increment is performed only on the 7 or 8 lsbs of the pointer depending on the selected data structure obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 72/106 size. it rolls over from 7fh to 00h or from ffh to 80h depending on the msb of the last data address received. then after that last byte has been effectively written or read in ram at lsb address 7fh or ffh, the edf flag is set and an interrupt is generated if ede is set. the transfer is terminated by the master generating a stop condition. 11.4 ddc/ci factory alignment interface refer to the cr, sr1 and sr2 registers in section 11.6 for the bit definitions. the ddc/ci interface works as an i/o interface between the microcontroller and the ddc2bi, hdcp, e-ddc or factory alignment protocols. it receives and transmits data in slave i2c mode using an interrupt or polled handshaking. the interface is connected to the i2c bus through a data pin (sdad) and a clock pin (scld) configured as an open-drain output. the ddc/ci interface has five internal register locations. two of them are used to initialize the interface: 1. two own address registers oar1 and oar2 2. control register cr the following four registers are used during data transmission/reception: 1. data register dr 2. control register cr 3. status register 1 sr1 4. status register 2 sr2 the interface decodes an i2c or ddc2bi address stored by soft ware in either oar register and/or the ddc/ci address (6eh/6fh) as its default hardware address. after a reset, the interface is disabled. 11.4.1 i2c modes the interface operates in slave transmitter/receiver modes. the master generates both start and stop conditions. the i2c clock (scl) is always received by the interface from a master, but the interface is able to stretch the clock line. the interface can recognize its two programmable addresses (7-bit) and its default hardware address (ddc/ci address: 6eh/6fh). the ddc/ci address detection may be enabled or disabled by software. it never recognizes the start byte (01h) whatever its own address is. slave mode as soon as a start condition is detected, the address is received from the sda line and sent to the shift register where it is compared to the programmable addresses or to the ddc/ci address (if selected by software). address not matched : the interface ignores it and waits for another start condition. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 73/106 address matched : the following events occur in sequence: acknowledge pulse is generated if the ack bit is set evf and adsl bits are set an interrupt is generated if the ite bit is set. then the interface waits for a read of the sr1 register, holding the scl line low (see ev1 in section 11.5 ). next, the dr register must be read to determine from the least significant bit if the slave must enter receiver or transmitter mode. slave receiver following the address reception and after sr1 register has been read, the slave receives bytes from the sda line into the dr register via the internal shift register. after each byte, the following events occur in sequence: acknowledge pulse is generated if the ack bit is set the evf and btf bits are set an interrupt is generated if the ite bit is set then the interface waits for a read of the sr1 register followed by a read of the dr register, holding the scl line low (see ev2 in section 11.5 ). slave transmitter following the address reception and after sr1 register has been read, the slave sends bytes from the dr register to the sda line via the internal shift register. the slave waits for a read of the sr1 register followed by a write in the dr register, holding the scl line low (see ev3 in section 11.5 ). when the acknowledge pulse is received: the evf and btf bits are set an interrupt is generated if the ite bit is set. closing slave communication after the last data byte is transferred, a stop condition is generated by the master. the interface detects this cond ition and in this case: the evf and stopf bits are set an interrupt is generated if the ite bit is set. then the interface waits for a read of the sr2 register (see ev4 in section 11.5 ). error cases berr : detection of a stop or a start condition during a byte transfer. in this case, the evf and the berr bits are set and an interrupt is generated if the ite bit is set. if it is a stop condition, then the interface discards the data, releases the lines and waits for another start condition. if it is a start condition, then the interface discards the data and waits for the next slave address on the bus. af : detection of a non-acknowledge bit. in this case, the evf and af bits are set and an interrupt is generated if the ite bit is set. note: in both cases, the scl line is not held lo w. however, the sda line can remain low due to possible ?0? bits transmitted last. it is then necessary to release both lines by software. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 74/106 how to release the sda / scl lines set and subsequently clear the stop bit when btf is set. the sda/scl lines are released after the transfer of the current byte. other events adsl: detection of a start condition after an acknowledge time-slot. the state machine is reset and starts a new process. the adsl bit is set and an interrupt is generated if the ite bit is set. the scl line is stretched low. stopf: detection of a stop condition after an acknowledge time-slot. the state machine is reset. then the stopf flag is set and an interrupt is generated if the ite bit is set. 11.5 transfer sequencing figure 39. transfer sequencing legend : s = start, p = stop, a = acknowledge, na = non-acknowledge and evx = event (with interrupt if ite = 1) ev1: evf = 1, adsl = 1, cleared by reading register sr1. ev2: evf = 1, btf = 1, cleared by reading register sr1 followed by reading dr register. ev3: evf = 1, btf = 1, cleared by reading register sr1 followed by writing dr register. ev3-1: evf = 1, af = 1 and btf = 1, af is cleared by reading register sr2, btf is cleared by releasing the lines (write stop = 1, stop = 0 in register cr) or by writing to register dr (dr = ffh). note: if the lines are released by stop = 1, stop = 0, the subsequent ev4 is not seen. ev4: evf = 1, stopf = 1, cleared by reading register sr2. figure 40. events flag and interrupt generation obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 75/106 11.6 register description ddc control register (ddccr) read / write reset value: 0000 0000 (00h) bit [7:6] = reserved . forced to 0 by hardware. table 23. ddca register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0020h 00h r/w ddccra 0 0 pe ddcien 0 ack stop ite 0021h 00h r ddcsr1a evf 0 tra busy btf adsl 0 0 0022h 00h r ddcsr2a 0 0 0 af stopf 0 berr ddci f 0023h 00h r/w ddcoar1a add[7:0] 0024h 00h r/w ddcoar2a add[7:0] 0025h 00h r/w ddcdra dr[7:0] 0026h 00h r/w reserved 0027h 00h r/w ddcdcra 0 0 endcf endce edf ede wp hwp e table 24. ddcb register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0028h 00h r/w ddccrb 0 0 pe ddcien 0 ack stop ite 0029h 00h r ddcsr1b evf 0 tra busy btf adsl 0 0 002ah 00h r ddcsr2b 0 0 0 af stopf 0 berr ddcif 002bh 00h r/w ddcoar1b add[7:0] 002ch 00h r/w ddcoar2b add[7:0] 002dh 00h r/w ddcdrb dr[7:0] 002eh 00h r/w reserved 002fh 00h r/w ddcdcrb 0 0 endcf endce edf ede wp hwpe table 25. edid dma pointer configuration cell basic edid extended edid ddca 600h...67fh 680h...6ffh ddcb 700h...77fh 780h...7ffh 76543210 0 0 pe ddcien 0 ack stop ite obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 76/106 bit 5 = pe peripheral enable. this bit is set and cleared by software. 0: peripheral disabled 1: slave capability note: when pe=0, all the bits of the cr register and the sr register are reset. all outputs are released while pe=0 when pe=1, the corresponding i/o pins are selected by hardware as alternate functions. to enable the i 2 c interface, write the cr register twice with pe=1 as the first write only activates the interface (only pe is set). bit 4 = ddcien ddc/ci address detection enabled. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). the 6eh/6fh ddc/ci address is acknowledged. 0: ddc/ci address detection disabled 1: ddc/ci address detection enabled bit 3 = reserved. forced to 0 by hardware. bit 2 = ack acknowledge enable. this bit is set and cleared by software. it is also cleared by hardware when the interface is disabled (pe=0). 0: no acknowledge returned 1: acknowledge returned after an address byte or a data byte is received bit 1 = stop release i2c bus . this bit is set and cleared by software or when the interface is disabled (pe=0). slave mode: 0: nothing 1: release the scl and sda lines after the current byte transfer (btf=1). the stop bit has to be cleared by software. bit 0 = ite interrupt enable. this bit is set and cleared by software and cleared by hardware when the interface is disabled (pe=0). 0:interrupts disabled 1:interrupts enabled refer to figure 40 for the relationship between the events and the interrupt. scl is held low when the btf or adsl is detected. ddc status register 1 (ddcsr1) read only reset value: 0000 0000 (00h) bit 7 = evf event flag. this bit is set by hardware as soon as an event occurs. it is cleared by software reading sr2 register in case of error event or as described in figure 40 . it is also cleared by hardware when the interface is disabled (pe=0). 76543210 evf 0 tra busy btf adsl 0 0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 77/106 0: no event 1: one of the following events has occurred: ? btf=1 (byte received or transmitted) ? adsl=1 (either address matched in slave mode while ack=1) ? af=1 (no acknowledge received after byte transmission if ack=1) ? stopf=1 (stop condition detected in slave mode) ? berr=1 (bus error, misplaced start or stop condition detected) bit6 = reserved. forced to 0 by hardware. bit 5 = tra transmitter/receiver. when btf is set, tra=1 if a data byte has been transmitted. it is cleared automatically when btf is cleared. it is also cleared by hardware after detection of stop condition (stopf=1) or when the interface is disabled (pe=0). 0: data byte received (if btf=1) 1: data byte transmitted bit 4 = busy bus busy . this bit is set by hardware on detection of a start condition and cleared by hardware on detection of a stop condition. it indicates a communication in progress on the bus. this information is still up dated when the interfac e is disabled (pe=0). 0: no communication on the bus 1: communication ongoing on the bus bit 3 = btf byte transfer finished. this bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ite=1. it is cleared by software reading sr1 register followed by a read or write of dr register. it is also cleared by hardware when the interface is disabled (pe=0). following a byte transmission, this bit is set after reception of the acknowledge clock pulse btf is cleared by reading sr1 register followed by writing the next byte in dr register. following a byte reception, this bit is set afte r transmission of the acknowledge clock pulse if ack=1. btf is cleared by reading sr1 register followed by reading the byte from dr register. the scl line is held low while btf=1. 0: byte transfer not done 1: byte transfer succeeded bit 2 = adsl address matched (slave mode). this bit is set by hardware as soon as the received slave address match ed with the oarx registers cont ent or the ddc/ci address is recognized. an interrupt is generated if ite=1. it is cleared by software reading sr1 register or by hardware when the interface is disabled (pe=0). the scl line is held low while adsl=1. 0: address mismatched or not received 1: received address matched bit 1:0 = reserved . forced to 0 by hardware. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 78/106 ddc status register 2 (ddcsr2) read only reset value: 0000 0000 (00h) bit [7:5] = reserved. forced to 0 by hardware. bit 4 = af acknowledge failure . this bit is set by hardware when no acknowledge is returned. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while af=1. 0: no acknowledge failure 1: acknowledge failure bit 3 = stopf stop detection. this bit is set by hardware when a stop condition is detected on the bus after an acknowledge (if ack=1). an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while stopf=1. 0: no stop condition detected 1: stop condition detected bit 2 = reserved. forced to 0 by hardware. bit 1 = berr bus error. this bit is set by hardware when the interface detects a misplaced start or stop condition. an interrupt is generated if ite=1. it is cleared by software reading sr2 register or by hardware when the interface is disabled (pe=0). the scl line is not held low while berr=1. 0: no misplaced start or stop condition 1: misplaced start or stop condition bit 0 = ddcif ddc/ci address detected. this bit is set by ha rdware when the ddc/ci address (6eh/6fh) is detected on the bus while ddcien=1. it is cleared by hardware when a stop condition (stopf=1) is detected, or when the interface is disabled (pe=0). 0: no ddc/ci address detected on bus 1: ddc/ci address detected on bus ddc data register (ddcdr) read / write reset value: 0000 0000 (00h) bits [7:0]= d7-d0 8-bit data register. these bits contain the byte to be received or transmitted on the bus. 76543210 0 0 0 af stopf 0 berr ddcif 76543210 d7 d6 d5 d4 d3 d2 d1 d0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 display data channel interfaces (ddc) 79/106 transmitter mode: byte transmission start automatically when the software writes in the dr register. receiver mode: the first data byte is received automatically in the dr register using the least significant bit of the address. then, the next data bytes are received one by one after reading the dr register. ddc own address register 1 (ddcoar1) read / write reset value: 0000 0000 (00h) bit [7:1] = add7-add1 interface address . these bits define the i 2 c bus programmable address of the interface. they are not cleared when the interface is disabled (pe=0). bit 0 = reserved . forced to 0 by hardware. ddc own address register 2 (ddcoar2) read / write reset value: 0000 0000 (00h) bit 7:1 = add7-add1 interface address . these bits define the i 2 c bus programmable address of the interface. they are not cleared when the interface is disabled (pe=0). bit 0 = reserved. forced to 0 by hardware. ddc2b control register (ddcdcr) read / write reset value: 0000 0000 (00h) bit [7:6] = reserved. forced by hardware to 0. bit 5 = endcf end of communication interrupt flag . this bit is set by hardware and cleared by software. 0: nack or stop condition not met in read mode. 1: nack or stop condition met in read mode. bit 4= endce end of communication interrupt enable . this bit is set and cleared by software. 0: end of communication interrupt disabled. 1: end of communication interrupt enabled. 76543210 add7 add6 add5 add4 add3 add2 add1 add0 76543210 add7 add6 add5 add4 add3 add2 add1 add0 76543210 0 0 endcf endce edf ede wp ddc2bpe obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
display data channel interfaces (ddc) ST7FLCD1 80/106 bit 3= edf end of download interrupt flag . this bit is set by hardware and cleared by software. 0: download not started or not completed yet. : 1download completed. last byte of data structure (relative address 7fh or ffh) has been stored or read in ram. bit 2 = ede end of download interrupt enable . this bit is set and cleared by software. 0: end of download interrupt disabled. 1: end of download interrupt enabled. bit 1 = wp write protect . this bit is set and cleared by software. 0: enable writes to the ram. 1: disable dma write transfers and protect the ram content. cpu writes to the ram are not affected. bit 0 = ddc2bpe. ddc2b peripheral enable. this bit is set and cleared by software. 0: release the sda port pin and ignore scl port pin. the other bits of the dcr are left unchanged. 1: enable the ddc interface and respond to the ddc2b protocol. note: when ddc2bpe = 1, all the bits of the d cr register are locked and cannot be changed. the desired configuration ther efore must be written in th e dcr register with ddc2bpe = 0 and then set the ddc2bpe bit in a second step. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 watchdog timer (wdg) 81/106 12 watchdog timer (wdg) the watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen lo gical conditions, which causes the application program to abandon its normal sequence. the watchdog circuit generates an mcu reset when the programmed time period expires, unless the program refreshes the counter?s contents before the t6 bit is cleared. in addition, a second counter prevents the watchdog register from being updated at intervals that are too close. 12.1 main features programmable timer (64 increments of 50000 cpu cycles) programmable reset reset (if watchdog enabled) when the t6 bit reaches zero reset (if watchdog enabled) on halt instruction lock-up counter for preventing short time refreshes figure 41. watchdog block diagram 12.2 main watchdog counter the counter value stored in the cr register (bits t[6:0]), is decremented every 50000 clock cycles, and the length of the time out period can be programmed by the user in 64 increments. if the watchdog is enabled (bit wdga is set) a nd when the 7-bit timer (bits t[6:0]) rolls over from 40h to 3fh (t6 is cleared), it initiates a reset cycle pulling low the reset pin for typically 500 ns: the wdga bit is set (watchdog enabled) bit t6 is set to prevent generating an immediate reset bits t[5:0] contain the number of increments which represents the time delay before the watchdog produces a reset. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
watchdog timer (wdg) ST7FLCD1 82/106 following a reset, the watchdog is disabled. once activated it cannot be disabled, except by a reset. the t6 bit can be used to generate a software re set (the wdga bit is set and the t6 bit is cleared). the application program must write in the cr register at regular intervals during normal operation to prevent an mcu reset. the value to be stored in the cr register must be between ffh and c0h (see ta b l e 2 6 ). 12.3 lock-up counter an 8-bit counter starts after a reset or by writing to the cr register. it disables the writing of the cr register during the next 256 cycles of cpu clock (typical value of 32 s at 8 mhz). if a writing order takes place during this time, this 8-bit counter is reset but not the main watchdog downcounter (no writing to the cr register occurs). thus after several too close writings of the cr register, the main downcounter reaches the reset value and a reset occurs. if the cr register is normally refreshed every 32 s or more, write commands are always enabled. 12.4 interrupts none. table 26. watchdog timing (f cpu = 8 mhz) cr register initial value wdg timeout (ms) lock-up timeout ( s) maximum ffh 400 32 minimum c0h 6.250 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 watchdog timer (wdg) 83/106 12.5 register description bit 7 = wdga activation bit . this bit is set by software and only cleared by hardware after a reset. when wdga = 1, the watchdog can generate a reset. 0: watchdog disabled 1: watchdog enabled bits [6:0] = t[6:0] 7-bit timer (msb to lsb). these bits contain the decremented value. a rese t is produced when it rolls over from 40h to 3fh (t6 is cleared). table 27. watchdog register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 001bh 7f r/w wdgcr wdga t[6:0] 76543 2 1 0 wdga t6 t5 t4 t3 t2 t1 t0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
8-bit timer (tima) ST7FLCD1 84/106 13 8-bit timer (tima) timer a is an 8-bit programmable free-running downcounter driven by a programmable prescaler. this block also has a buzzer. the block diagram is shown in figure 42 . 13.1 main features programmable prescaler: f cpu divided by 1, 8 or 64 overflow status flag and maskable interrupt reduced power mode independent buzzer output with 4 programmable tones figure 42. timer a (tima) block diagram 13.2 functional description timer a is a 8-bit downcounter and its associated 8-bit register is loaded as start value of the downcounter each time it has reached the 00h value. a flag indicates that the downcounter rolled over the 00h value. the buzzer has 4 distinct tones. before the downcounter prescaler block, the frequency is divided by 2048. f timer = f cpu /2048 note: in one-shot mode, the counter stops at 00h (low power state). obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 8-bit timer (tima) 85/106 13.3 register description bits [7:6] = tb[1:0] time base period selection these bits are set and cleared by software. 00: time base period = t timer (256 s @ 8 mhz) 01: time base period = t timer x 8 (2048 s @ 8 mhz) 10: time base period = t timer x 64 (16384 s @ 8 mhz) 11: reserved bit 5 = ovf timer overflow flag. this bit is set by hardware. an interrupt is generated if ovfe = 1. it must be cleared by reading the timcsra register. 0: no timer overflow. 1: the free-running downcounter reached 00h. bit 4 = ovfe timer overflow interrupt enable. this bit is set and cleared by software. 0: interrupt disabled 1: interrupt enabled bit 3 = tar timer auto-reload this bit is set and cleared by software. 0: one-shot mode. the counter restarts after a write in the timcpra register. 1: auto-reload mode. the counter is reloaded automatically by the timcpra register after the downcounter reaches 00h. bits [2:1] = buz[1:0] buzzer tone selection these bits are set and cleared by software. 00: time base frequency = f timer /16 (244 hz @ 8 mhz) 01: time base frequency = f timer /8 (488 hz @ 8 mhz) 10: time base frequency = f timer /4 (976 hz@ 8 mhz) 11: time base frequency = f timer /2 (1.95 khz @ 8 mhz) table 28. timer controller register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000dh 00h r/w timcsra tb1 tb0 ovf ovfe tar buz1 buz0 buze 000eh 00h r/w timcpra pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 76543 2 1 0 tb1 tb0 ovf ovfe tar buz1 buz0 buze obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
8-bit timer (tima) ST7FLCD1 86/106 bit 0 = buze buzzer enable this bit is set and cleared by software. 0: buzzer disabled 1: buzzer enabled. it has priority over any other alternate function mapped onto the same pin (pwm). timer a counter preload register (timcpra) read/write reset value: (00h) bits [7:0] = pr[7:0] counter preload data these bits are set and cleared by software. they are used to hold the reload value which is immediately loaded in the counter. note: the n number loaded in timcpra register corresponds to a time of (n + 1) x period timer. the "00" value is prohobited. 76543 2 1 0 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 8-bit timer with external trigger (timb) 87/106 14 8-bit timer with external trigger (timb) timer b is an 8 bit-programmable free-running downcounter, driven by a programmable prescaler. an external signal can also trigger the countdown. the timer b block diagram is shown in figure 43 . 14.1 main features programmable prescaler: f cpu divided by 1, 8 or 16 overflow status flag and maskable interrupt auto reload capability an external signal with programmable polarity can trigger the count-down figure 43. external timer block diagram 14.2 functional description the 8 bit-downcounter timer counts from a start value down to 00h. the start value is preloaded from the associated 8-bit timcprb register every time it is written, or when the counter has reached the 00h value (auto reload feature) if the tar bit is set. the ovf flag is set when the downcounter reaches 00h. an interrupt is generated if the ovfe bit is set. when the ext bit is set, an external signal edge triggers the countdown start. the edg bit controls the rising or falling signal edge. on ce detected, the select ed edge sets the eef flag, preloads the downcounter with the start value and starts the countdown as usual. during the countdown, the downcounter c annot be retriggered and subsequent pulses occurring after the countdown has started are ignored until the counter reaches 00h. there are four possible operating modes as described in ta b l e 2 9 . obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
8-bit timer with external trigger (timb) ST7FLCD1 88/106 note: 1 the downcounter value cannot be read. 2 change the ext value to exit the external one-shot mode. timer b control status register (timcsrb) read/write reset value: (00h) bits [7:6] = tb[1:0] time base period selection these bits are set and cleared by software. 00: time base period = t timer (16 s @ 8 mhz) 01: time base period = t timer x 8 (128 s @ 8 mhz) 10: time base period = t timer x 16 (256 s @ 8 mhz) 11: reserved bit 5 = ovf timer overflow flag this bit is set by hardware. an interrupt is generated if ovfe = 1. it must be cleared by reading the timcsrb register. 0: no timer overflow 1: the free running downcounter rolled over from 00h bit 4 = ovfe timer overflow interrupt enable this bit is set and cleared by software. 0: interrupt disabled table 29. timer operating mode tar ext timer mode 00 one-shot after the timcprb register write (no auto reload) 01 one-shot after the external signal detection (no auto reload). only the very first external pulse triggers the countdown ( note 2 ) 10 downcounter auto-reload when 00h reached downcounter reloaded with timcprb register value, count-down restarts 11 one-shot for each external signal detection. downcounter preloaded with timcprb when 00h reached. countdown restarts after the next external signal detection. table 30. timer controller register map address reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0038h 00h r/w timcsrb tb1 tb0 ovf ovfe tar ext edg eff 0039h 00h r/w timcprb pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 7 0 tb1 tb0 ovf ovfe tar ext edg eff obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 8-bit timer with external trigger (timb) 89/106 1: interrupt enabled bit 3 = tar timer auto reload this bit is set and cleared by software. 0: one-shot mode. the counter restarts after writing to the timcprb register. 1: auto reload mode. the counter is reloaded automatically from the timcprb register when 00h is reached. bit 2 = ext external trigger this bit is set and cleared by software. 0: internal. the downcounter restarts after writing to the timcprb register or after an auto- reload if the tar bit is set 1: external. the downcounter is preloaded with the timcprb register but the countdown starts only when the external signal is detected, not by writng to the timcprb register. bit 1 = edg external signal edge this bit is set and cleared by software. 0: a rising edge signal starts the count-down. 1: a falling edge signal starts the count-down bit 0 = eef external event flag this bit is set and cleared by hardware when an external event occurs. this bit is cleared when the counter reaches ?00h? in external mode or when the value of the ext bit is changed by software. in internal mode, this bit is set when the selected edge is detected (the edg bit) but it is never cleared by itself. it may then be used as a simple edge detector. timer b counter preload register (timcprb) read/write reset value: (01h) bits [7:0] = pr[7:0] counter preload data this bit is set and cleared by software. bits hold the reload value which is loaded in the counter either immediately (ext = 0) or when the external signal is detected (ext = 1). note: the n number loaded in timcprb register corresponds to a time of (n + 1) x period timer. the "00" value is prohibited. 76543 2 1 0 pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
infrared preprocessor (ifr) ST7FLCD1 90/106 15 infrared preprocessor (ifr) the infrared preprocessor measures the intervals between two adjacent edges of a serial input. 15.1 main features interval measurement between 2 edges (time base = 12.5 khz) @ f cpu = 8 mhz choice of active edge glitch filter overflow detection (20.4 ms = 255/12.5 khz) maskable interrupt 15.2 functional description the ir preprocessor measures the interval between two adjacent edges of the ifr input signal. the posed and neged bits determine if the intervals of interest involve: consecutive positive edges negative edges or any pair of edges as described in ta bl e 3 1 . figure 44. ifr block diagram the measurement is a count resulting from a 12.5 khz clock. therefore, any pulse width that is less than 80 s cannot be detected. whenever an edge of the specified polarity is detected, the count accumulated since the previously detected edge is latched into the ifrdr register, an interrupt is generated and the counter is reset. if an edge is not detected within 20.4 ms (f cpu = 8 mhz) and the count reaches its maximum value of 255, it is latched immediately. the internal interrupt flag and also an internal overflow flag are set.the latch content remains unchanged as long as the overflow flag is set. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 infrared preprocessor (ifr) 91/106 the count stored in the latch register is overwritten in case the microcontroller fails to execute the read be fore the next edge. writing to the if rdr register clears the interrupt and internal overflow flag. the ifr input signal is preprocessed by a spike filter. this filter re moves all pulses with a positive level that lasts less than 2 s or 160 s, depending on the flsel bit. the negative level can be of any duration and is never filtered out. note: if the interrupt is enabled but no signal is detected, an interrupt occurs every 20.4 ms. 15.3 register description infrared data register (ifrdr) read/write reset value: (00h) bits [7:0] = ir[7:0] infra red pulse width the 8-bit counter value is transferred in this register when an expected edge occurs on the ifr pin or when the counter overflows. a write to this register resets the internal overflow flag. infrared control register (ifrcr) read/write reset value: (00h) bits [7:5] = reserved. forced by hardware to 0. bit 4 = ite interrupt enable 0: interrupt disabled 1: interrupt enabled. it is generated when an edge (falling and/or ri sing depending on bits posed and neged) occurs or after a counter overflow. bit 3 = flsel spike filter pulse width selection 0: filter positive pulses narrower than 2 s 1: filter positive pulses narrower than 160 s bits [2:1] = posed, neged edge selection for the duration measurement 76543 2 1 0 ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir0 76543 2 1 0 0 0 0 ite flsel posed neged 0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
infrared preprocessor (ifr) ST7FLCD1 92/106 bit 0 = reserved. forced by hardware to 0. table 31. duration measurement posed neged count latch at... 0 0 when count reaches 255 0 1 negative transition of ifr or when count reaches 255 1 0 positive transition of ifr or when count reaches 255 1 1 positive or negative transition of ifr or when count reached 255 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 registers 93/106 16 registers 16.1 register description name register (namer) read only reset value: 00h bits [7:0] = n[7:0] circuit name this register indicates the version number of the circuit. the current value is 01h. 76543 2 1 0 n[7:0] table 32. ST7FLCD1 register summary address reset register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000h 00h r namer 0001h00h miscr0000 0 pa 5 ov d pa 4 ov d 0 0002h 00h r/w padr padr[7:0] 0003h 00h r/w paddr paddr[7:0] 0004h 00h r/w pbdr pbdr[7:0] 0005h 00h r/w pbddr pbddr[7:0] 0006h 00h r/w pcdr pcdr[7:0] 0007h 00h r/w pcddr pcddr[7:0] 0008h 00h r/w pddr pddr[7:0] 0009h 00h r/w pdddr pdddr[7:0] 000ah 00h r adcdr ad[7:0] 000bh 00h r/w adccsr coco 0 adon 0 0 0 ch[1:0] 000ch 00h r/w itrfre 0 0 itb edge itblat itbite ita edge italat itaite 000dh 00h r/w timcsra tb1 tb0 ovf ovfe tar buz1 buz0 buze 000eh 00h r/w timcpra pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 000fh 00h r/w pwmdcr0 dcr0[7:0] 0010h 00h r/w pwmdcr1 dcr1[7:0] 0011h 00h r/w pwmdcr2 dcr2[7:0] 0012h 00h r/w pwmdcr3 dcr3[7:0] 0013h 00h r/w pwmcra oe3 oe2 oe1 oe0 op3 op2 op1 op0 0014h ffh r/w pwmarra arra[7:0] 0015h 00h r/w pwmdcr4 dcr4[7:0] obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
registers ST7FLCD1 94/106 0016h 00h r/w pwmdcr5 dcr5[7:0] 0017h 00h r/w pwmcrb 0 0 oe5 oe4 0 0 op5 op4 0018h ffh r/w pwmarrb arrb[7:0] 0019h 00h r/w fcsr 001ah reserved 001bh 7f r/w wdgcr wdga t[6:0] 001ch 00h r/w i2ccr 00 pe 0 start ack stop ite 001dh 00h r i2csr evf af tra 0 btf 0 m/idl sb 001eh 00h r/w i2cccr fm/sm filterof f cc5 ...cc0 001fh 00h r/w i2cdr dr[7:0] 0020h 00h r/w ddccra 0 0 pe ddccie n 0 ack stop ite 0021h 00h r ddcsr1a evf 0 tra busy btf adsl 0 0 0022h00hrddcsr2a000afstopf0berr ddcci f 0023h 00h r/w ddcoar1a add[7:0] 0024h 00h r/w ddcoar2a add[7:0] 0025h 00h r/w ddcdra dr[7:0] 0026h reserved 0027h 00h r/w ddcdcra 0 0 endc f endce edf ede wp hwpe 0028h 00h r/w ddccrb 0 0 pe ddccie n 0 ack stop ite 0029h 00h r ddcsr1b evf 0 tra busy btf adsl 0 0 002ah00hrddcsr2b000afstopf0berr ddcci f 002bh 00h r/w ddcoar1b add[7:0] 002ch 00h r/w ddcoar2b add[7:0] 002dh 00h r/w ddcdrb dr[7:0] 002eh reserved 002fh 00h r/w ddcdcrb 0 0 endc f endce edf ede wp hwpe 0030h 00h r/w dmcr wdgo ff mtr bc2 bc1 bc0 bir biw aie 0031h 10h r dmsr wp ste stf rst brw bk2f bk1f af 0032h ffh r/w dmbk1h bk1h7 bk1h6 bk1h5 bk1h4 bk1h3 bk1h2 bk1h1 bk1h0 0033h ffh r/w dmbk1l bk1l7 bk1l6 bk1l5 bk1l4 bk1l3 bk1l2 bk1l1 bk1l0 table 32. ST7FLCD1 register summary (continued) address reset register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 registers 95/106 0034h ffh r/w dmbk2h bk2h7 bk2h6 bk2h5 bk2h4 bk2h3 bk2h2 bk2h1 bk2h0 0035h ffh r/w dmbk2l bk2l7 bk2l6 bk2l5 bk2l4 bk2l3 bk22l bk2l1 bk2l0 0036h 00h r ifrdr ir7 ir6 ir5 ir4 ir3 ir2 ir1 ir0 0037h00hr/wifrcr000iteflsel pose d nege d - 0038h 00h r/w timcsrb tb1 tb0 ovf ovfe tar ext edg eef 0039h 01h r/w timcprb pr7 pr6 pr5 pr4 pr3 pr2 pr1 pr0 003ah reserved table 32. ST7FLCD1 register summary (continued) address reset register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
electrical characteristics ST7FLCD1 96/106 17 electrical characteristics the ST7FLCD1 device contains circuitry to pr otect the inputs against damage due to high static voltage or electric field. nevertheless it is advised to take normal precautions and to avoid applying to this high impedance voltage circuit any voltage higher than the maximum rated voltages. it is recommended for proper operation that v in and v out be constrained to the range: v ss < ( v in or v out ) > v dd to enhance reliability of operat ion, it is recommended to connect unused inputs to an appropriate logic voltage level such as v ss or v dd . all the voltages in the following table, are referenced to v ss . 17.1 absolute maximum ratings table 33. absolute maximum ratings symbol ratings value unit v dd recommended supply voltage -0.3 to +6.0 v v in input voltage v ss -0.3 to v dd + 0.3 v v ain analog input voltage (a/d converter) v ss -0.3 to v dd + 0.3 v v out output voltage v ss -0.3 to v dd + 0.3 v i in input current -10 to +10 ma i out output current -10 to +10 ma i inj accumulated injected current of all i/o pins (vdd, vss) 40 ma t a operating temperature range 0 to +70 o c t stg storage temperature range -65 to +150 o c t j junction temperature 150 o c pd power dissipation tbd mw esd esd susceptibility 2000 v obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 electrical characteristics 97/106 17.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x j a ) (1) where: t a is the ambient temperature in c, j a is the package junction-to-ambient thermal resistance, in c/w p d is the sum of p int and p i/o , p int is the product of i dd and v dd , expressed in watts. this is the chip internal power p i/o represents the power dissipation on input and output pins; user determined. for most applications p i/o

electrical characteristics ST7FLCD1 98/106 17.4 ac/dc electrical characteristics all voltages are referred to v ss and t a = 0 to +70 o c (unless otherwise specified) table 35. ac/dc electrical characteristics symbol parameter conditions min. typ. max. unit general v dd operating supply voltage 4.5 5 5.5 v operating voltage for flash access read 3.8 v write/erase 4.5 5.5 v i dd cpu run mode i/o in input mode v dd = 5v f cpu = 8 mhz, ta = 20c 14 18 ma cpu wait mode 12 18 ma cpu halt mode 1 10 a control timing f osc external frequency 24 27 mhz f cpu internal frequency 8 9 mhz t bu startup time built-up time crystal resonator 8 20 ms t rl external reset input pulse width 1000 ns t porl internal power reset duration 4096 t cpu t powl watchdog reset output pulse width 500 ns t dog watchdog time-out f cpu = 8 mhz 50000 6.25 320000 0 400 t cpu ms t ilil interrupt pulse period see note 1 t cpu t oxov crystal oscillator start-up time 50 ms t ddr power-up rise time v dd min. 1 100 ms standard i/o port pins v ol output low level voltage port a[7:6,3:0], port b[3:0], push pull i ol = 2 ma and v dd = 5 v 0.4 v v ol output low level voltage port c[1:0] open drain i ol = 4 ma and v dd = 5 v 0.4 v v ol output low level voltage port a[5:4] (see note 2) i ol = 8 ma and v dd = 5 v i ol = 2 ma and v dd = 5 v 0.4 v v ol output low level voltage port d[7:0] open drain i ol = 4 ma and v dd = 5 v 0.4 v v oh output high level voltage port a[7:6,3:0], port b[3:0], push pull i oh = 2 ma v dd -0.8 v v oh output high level voltage port a[5:4] i oh = 2 ma i oh = 8 ma v dd -0.8 v obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 electrical characteristics 99/106 note: 1 the minimum period t ilil should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 cycles. 2 for the case of i ol = 8 ma, 8 ma output current if corresponding overdrive bit = 1 in miscr register. 3 output high level by means of external pull-up resistor. 17.5 power on/off electrical specifications v oh output high level voltage port c[1:0], port d (see note 3) v dd v v ih input high level voltage port a [7:0], port b [3:0], port c [1:0], port d[7:0], reset leading edge 0.7 * v dd v dd v v il input low level voltage port a [7:0], port b [3:0], port c [1:0], port d[7:0], reset trailing edge v ss 0.2 * v dd v i il i/o ports hi-z leakage current port a[7:0], port b[3:0], port c[1:0], port d[7:0], reset 10 a c out c in capacitance: ports (as input or output), reset 128 pf irpu pull-up resistor current v dd = 5v v in = v ss t = 25c 30 60 100 a table 35. ac/dc electrical characteristics (continued) table 36. power on/off electrical specifications symbol parameter conditions min. typical max. unit v trh power on/off reset trigger v dd rising edge v dd variation 50mv/ms 3.8 4 4.2 v v trl power on/off reset trigger v dd rising edge v dd variation 50mv/ms 3.75 4 4.2 v v trm v dd minimum for power on/off reset active v dd variation 50mv/ms tbd v obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
electrical characteristics ST7FLCD1 100/106 17.6 8-bit analog-to-digital converter 17.7 i2c/ddc bus electrical specifications table 37. 8-bit analog-to-digital converter symbol parameter conditions min. typical max. unit f adc analog control frequency v dd = 5 v 2 mhz | tue| total unadjusted error f cpu = 8 mhz, f adc = 2mhz v dd = 5 v 0 1 2 lsb oe offset error -2 1 2 ge gain error -2 1 2 |dle| differential linearity error 0 0.5 1 |ile| integral linearity error 0 1 2 v ain conversion range voltage v ss v dd v i adc a/d conversion supply current f cpu = 8 mhz, f adc = 2mhz, v dd = 5 v 1 ma t stab stabilization time after enable adc 1 s t load sample capacitor loading time 1 4 s 1/fadc t conv conversion time 2 8 s 1/fadc r ain external input resistor 15 k r adc internal input resistor 1.5 k c sample sample capacitor 6 pf table 38. i 2 c/ddc bus electrical specifications symbol parameter standard mode fast mode unit min. max. min. max. v hys hysteresis of schmitt trigger inputs v fixed input levels na na 0.2 vdd-related input levels na na 0.05 v dd t sp pulse width of spikes which must be suppressed by the input filter na na 0 ns 50 ns ns t of output fall time from vih min to vil max with a bus capacitance from 10 pf to 400 pf ns with up to 3 ma sink current at vol1 250 20+0.1 cb 250 with up to 6 ma sink current at vol2 na na 20+0.1 cb 250 obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 electrical characteristics 101/106 note: na = not applicable cb = capacitiance of one bus in pf 17.8 i 2 c/ddc bus timings i input current each i/o pi n with an input voltage between 0.4v and 0.9 v dd max -10 10 -10 10 a c capacitance for each i/o pin 10 10 pf table 38. i 2 c/ddc bus electrical specifications symbol parameter standard mode fast mode unit min. max. min. max. table 39. i 2 c/ddc bus electrical specifications symbol parameter standard mode fast mode unit min. max. min. max. t buf bus free time between stop and start condition 4.7 1.3 ms t hd:sta hold time start condition. after this period, the first clock pulse is generated 4.0 0.6 s t low low period of the scl clock 4.7 na 1.3 s t high high period of the scl clock 4.0 0.6 s t su:sta set-up time for a repeated start condition 4.7 0.6 ns t hd:dat data hold time 0 (1) 00.9 (2) ns t sd:dat data set-up time 250 100 ns t r rise time of both sda and scl signals 1000 20+0.1 cb 300 ns t f fall time of both sda and scl signals 300 20+0.1 cb 300 ns t su:sto input current each i/o pi n with an input voltage between 0.4v and 0.9 v dd max 4.0 0.6 a c capacitance load for each bus line 400 400 pf 1. the device must internally provide a hol d time of at least 300 ns for the sda si gnal in order to bridge the undefined region of the falling edge of scl 2. the maximum hold time of the start cond ition has only to be met if the interface does not stretch the low period of scl signal cb = total capacitance of the bus line in pf i 2 c parameters compliant with i 2 c bus specifications up to 400 khz only. fa ster speeds are at us er responsibility. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
electrical characteristics ST7FLCD1 102/106 figure 45. i2c bus timing obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 package mechanical data 103/106 18 package mechanical data figure 46. 28-pin small outline package (so28) table 40. jedec standard package dimensions dimensions mm inch min. typ. max. min. typ. max. a2.650.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 o (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 o (max.) obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
package mechanical data ST7FLCD1 104/106 18.1 lead-free packaging to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 revision history 105/106 19 revision history table 41. document revision history date revision changes may-2002 2.1 addition of section 5.5 and section 5.6 19-aug-2002 2.2 update of chapter number ing system. update of figure 2: 28-pin small outline package (so28) pinout , figure 12: typical icp interface , pin 14 becomes pa6/ita/extrig. addition of miscr register (0001h) and update of ddc2b control register data. lock- up counter info added in section 12: watchdog timer (wdg) . buzzer output info added in section 13: 8-bit timer (tima) . modification of oscillator frequency from 24 mhz to maximum of 27 mhz, fast i2c mode up to 800 khz (for certain applications), section 8: pwm generator , section 10.5: transfer sequencing and section 11.6: transfer sequencing . addition of section 17: electrical characteristics and section 19: revision history . 24-sep-2002 2.3 modification of figure 4: program memory map . 14-oct-2002 2.4 modification of figure 4: program memory map and table 34: summary of modifications . 4-dec-2002 2.5 modification of i2c clock control register. 6-feb-2003 2.6 change of vtrh and vtrl values in section 17.4: ac/dc electrical characteristics . 11-feb-2002 2.7 addition of section 1.5: external connections . update of ddc2b control register (bit 3) information in section 11.7: register description . change of vdd values in section 17.4: ac/dc electrical characteristics . 2-sep-2003 2.8 modification of values in section 17.4: ac/dc electrical characteristics , section 17.5: poweron/off electrical specifications and section 17.6: 8-bit analog-to-digital converter . 13-apr-2004 2.9 addition of voh row in standard i/o port pins on page 89 . addition of note 1 on page 9 . 9-feb-2005 2.10 update of section 6.1.2: crystal oscillator mode on page 32 . 4-nov-2008 4.0 new template applied, revision number corrected. no change to technical content obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)
ST7FLCD1 106/106 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2008 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com obsolete product(s) - obsolete product(s) obsolete product(s) - obsolete product(s)

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